Patents by Inventor Shawn Nikoukary

Shawn Nikoukary has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods for avoiding parasitic capacitance in an integrated circuit package
    Patent number: 8288269
    Abstract: An integrated circuit package substrate includes a first and an additional electrically conductive layer separated from each other by an electrically insulating layer, a contact pad formed in the first electrically conductive layer for making a direct connection between the integrated circuit package substrate and a printed circuit board, and a cutout formed in the additional electrically conductive layer wherein the cutout encloses an area that completely surrounds the contact pad for avoiding parasitic capacitance between the additional electrically conductive layer and the printed circuit board.
    Type: Grant
    Filed: October 4, 2011
    Date of Patent: October 16, 2012
    Assignee: LSI Corporation
    Inventors: Jeffrey Hall, Shawn Nikoukary, Amar Amin, Michael Jenkins
  • Methods for Avoiding Parasitic Capacitance in an Integrated Circuit Package
    Publication number: 20120021599
    Abstract: An integrated circuit package substrate includes a first and an additional electrically conductive layer separated from each other by an electrically insulating layer, a contact pad formed in the first electrically conductive layer for making a direct connection between the integrated circuit package substrate and a printed circuit board, and a cutout formed in the additional electrically conductive layer wherein the cutout encloses an area that completely surrounds the contact pad for avoiding parasitic capacitance between the additional electrically conductive layer and the printed circuit board.
    Type: Application
    Filed: October 4, 2011
    Publication date: January 26, 2012
    Applicant: LSI CORPORATION
    Inventors: Jeffrey Hall, Shawn Nikoukary, Amar Amin, Michael Jenkins
  • Device for avoiding parasitic capacitance in an integrated circuit package
    Patent number: 8049340
    Abstract: An integrated circuit package substrate includes a first and an additional electrically conductive layer separated from each other by an electrically insulating layer, a contact pad formed in the first electrically conductive layer for making a direct connection between the integrated circuit package substrate and a printed circuit board, and a cutout formed in the additional electrically conductive layer wherein the cutout encloses an area that completely surrounds the contact pad for avoiding parasitic capacitance between the additional electrically conductive layer and the printed circuit board.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: November 1, 2011
    Assignee: LSI Corporation
    Inventors: Jeffrey Hall, Shawn Nikoukary, Amar Amin, Michael Jenkins
  • DEVICE FOR AVOIDING PARASITIC CAPACITANCE IN AN INTEGRATED CIRCUIT PACKAGE
    Publication number: 20070222084
    Abstract: An integrated circuit package substrate includes a first and an additional electrically conductive layer separated from each other by an electrically insulating layer, a contact pad formed in the first electrically conductive layer for making a direct connection between the integrated circuit package substrate and a printed circuit board, and a cutout formed in the additional electrically conductive layer wherein the cutout encloses an area that completely surrounds the contact pad for avoiding parasitic capacitance between the additional electrically conductive layer and the printed circuit board.
    Type: Application
    Filed: March 22, 2006
    Publication date: September 27, 2007
    Inventors: Jeffrey Hall, Shawn Nikoukary, Amar Amin, Michael Jenkins
  • Device for minimizing differential pair length mismatch and impedance discontinuities in an integrated circuit package design
    Patent number: 7180011
    Abstract: A method of routing an integrated circuit package design includes steps of receiving as input at least a portion of an integrated circuit design including a differential pair of two electrical conductors, calculating a value of length mismatch between the two electrical conductors, calculating an added trace length to compensate for an impedance discontinuity of a shorter one of the two electrical conductors, and extending the shorter one of the two electrical conductors by routing the added trace length entirely inside an area surrounded by a contact pad that electrically terminates the shorter one of the two electrical conductors. The routing for the differential pair with the added trace length is generated as output in the integrated circuit design.
    Type: Grant
    Filed: March 17, 2006
    Date of Patent: February 20, 2007
    Assignee: LSI Logic Corporation
    Inventors: Jeffrey Hall, Shawn Nikoukary