Abstract: A technique for handling storage commands includes receiving, by an interface node of a data storage system, a first storage command. The interface node determines whether the first storage command is a head of queue (HOQ) command. In response to determining the first storage command is an HOQ command, the interface node increments a constrained command count and issues the first storage command to a first worker processor core for processing. In response to determining the first storage command is not an HOQ command, the interface node processes the first storage command as a non-HOQ command.

Abstract: Firmware is run in an emulated environment such that firmware is not embedded in its designed-for target device. Target device emulation software communicatively connects the firmware to the operating system in a manner so that communications sent from and received by the operating system are identical to communications that would be sent from and received by the operating system if the firmware were actually embedded in the target device instead of running in the emulated environment.

Abstract: A method includes monitoring power usage for a storage system that includes a set storage units at a first level of storage granularity and a set of storage sub-units at a second level of storage granularity, wherein the second level of storage granularity is finer than the first level of storage granularity. The method further includes assigning a non-uniform power budget to the set of storage units and adjusting a power budget for the storage sub-units according to the non-uniform power budget assigned to the storage units. A corresponding computer program product and computer system are also disclosed herein.

Abstract: Mechanisms are provided, in a Not AND (NAND) flash memory device, for providing hybrid error correction management. A NAND flash memory module and a node controller coupled to the NAND flash memory module are provided along with a hardware logic implemented error correction code (ECC) engine associated with the node controller. The node controller is configured to determine whether an error count is less than or equal to a first threshold number of error bits and, in response to the error count being less than or equal to the first threshold number of error bits, performing correction of the error bits by the hardware logic implemented ECC engine associated with the node controller. The node controller is also configured to forward uncorrected data to a software logic implemented ECC engine, in response to the error count being greater than the first threshold number of error bits.

Abstract: A technique for handling storage commands includes receiving, by an interface node of a data storage system, a first storage command. The interface node determines whether the first storage command is a head of queue (HOQ) command. In response to determining the first storage command is an HOQ command, the interface node increments a constrained command count and issues the first storage command to a first worker processor core for processing. In response to determining the first storage command is not an HOQ command, the interface node processes the first storage command as a non-HOQ command.

Abstract: An interface receives a command corresponding to a non-volatile memory. The interface determines whether a bypass mode is enabled and whether the command is a medium-access command. A primary processing node processes the command in response to determining at least one of the following: that the bypass mode is disabled or that the command is not a medium-access command. A secondary processing node processes the command, in response to determining that the bypass mode is enabled and that the command is a medium-access command.

Abstract: A method includes monitoring power usage for a storage system that includes a set storage units at a first level of storage granularity and a set of storage sub-units at a second level of storage granularity, wherein the second level of storage granularity is finer than the first level of storage granularity. The method further includes assigning a non-uniform power budget to the set of storage units and adjusting a power budget for the storage sub-units according to the non-uniform power budget assigned to the storage units. A corresponding computer program product and computer system are also disclosed herein.

Abstract: A method includes monitoring power usage for a storage system that includes a set storage units at a first level of storage granularity and a set of storage sub-units at a second level of storage granularity, wherein the second level of storage granularity is finer than the first level of storage granularity. The method further includes assigning a non-uniform power budget to the set of storage units and adjusting a power budget for the storage sub-units according to the non-uniform power budget assigned to the storage units. A corresponding computer program product and computer system are also disclosed herein.

Abstract: A method includes monitoring power usage for a storage system that includes a set storage units at a first level of storage granularity and a set of storage sub-units at a second level of storage granularity, wherein the second level of storage granularity is finer than the first level of storage granularity. The method further includes assigning a non-uniform power budget to the set of storage units and adjusting a power budget for the storage sub-units according to the non-uniform power budget assigned to the storage units. A corresponding computer program product and computer system are also disclosed herein.

Abstract: A method includes monitoring power usage for a storage system that includes a set storage units at a first level of storage granularity and a set of storage sub-units at a second level of storage granularity, wherein the second level of storage granularity is finer than the first level of storage granularity. The method further includes assigning a non-uniform power budget to the set of storage units and adjusting a power budget for the storage sub-units according to the non-uniform power budget assigned to the storage units. A corresponding computer program product and computer system are also disclosed herein.

Abstract: A method includes monitoring power usage for a storage system that includes a set storage units at a first level of storage granularity and a set of storage sub-units at a second level of storage granularity, wherein the second level of storage granularity is finer than the first level of storage granularity. The method further includes assigning a non-uniform power budget to the set of storage units and adjusting a power budget for the storage sub-units according to the non-uniform power budget assigned to the storage units. A corresponding computer program product and computer system are also disclosed herein.

Abstract: In a data storage system, a hierarchical data structure, such as a file system or a database, is utilized to organize a hierarchical arrangement of device containers corresponding to various device identifiers of the plurality of hardware components in the target hardware system, scripts corresponding to various packet types of communication packets in the target hardware system, and responses corresponding to various packet data in the communication packets in the target hardware system. In response to receipt by a hierarchical emulation engine of a communication packet during emulation of the target hardware system, the communication packet including a device identifier, packet type and packet data, a response to the communication packet is determined by traversing the hierarchical arrangement based on the device identifier, packet type and packet data of the communication packet. The determined response is then provided.

Abstract: A mechanism is provided for dynamic power and thermal capping in a flash storage system. A set of measurement values are received for the flash storage system, the set of measurement values comprising one or more of a set of current (I) measurement values, a set of voltage (V) measurement values, or a set of temperature (T) measurement values. An average current (Iavg) value from the set of current (I) measurements and, responsive to the average current (Iavg) value being greater than a predetermined maximum current (Imax) value, a determination is made as to whether a rate at which erase operations are performed for the flash storage system is greater than a predetermined minimum erase rate. Responsive to the rate at which erase operations are performed for the flash storage system being greater than the predetermined minimum erase rate, the rate at which erase operations are performed for the flash storage system are decreased by a predetermined value.

Abstract: To emulate a hardware component of a target hardware system including a plurality of hardware components, a component model of the hardware component is built, where the component model includes a register interface through which a host application provides inputs to and reads outputs from the component model, one or more parameter registers that hold values of state variables of the component model, and a state machine that models behavior of the hardware component without explicitly emulating logic implemented in the hardware component. During modeling of the hardware component utilizing the component model the component model is dynamically modified other than by modifying values of the state variables.

Abstract: Mechanisms are provided, in a Not AND (NAND) flash memory device, for providing hybrid error correction management. A NAND flash memory module and a node controller coupled to the NAND flash memory module are provided along with a hardware logic implemented error correction code (ECC) engine associated with the node controller. The node controller is configured to determine whether an error count is less than or equal to a first threshold number of error bits and, in response to the error count being less than or equal to the first threshold number of error bits, performing correction of the error bits by the hardware logic implemented ECC engine associated with the node controller. The node controller is also configured to forward uncorrected data to a software logic implemented ECC engine, in response to the error count being greater than the first threshold number of error bits.

Abstract: A method includes monitoring power usage for a storage system that includes a set storage units at a first level of storage granularity and a set of storage sub-units at a second level of storage granularity, wherein the second level of storage granularity is finer than the first level of storage granularity. The method further includes assigning a non-uniform power budget to the set of storage units and adjusting a power budget for the storage sub-units according to the non-uniform power budget assigned to the storage units. A corresponding computer program product and computer system are also disclosed herein.

Abstract: Mechanisms are provided, in a Not AND (NAND) flash memory device, for providing hybrid error correction management. A NAND flash memory module and a node controller coupled to the NAND flash memory module are provided along with a hardware logic implemented error correction code (ECC) engine associated with the node controller. The node controller is configured to determine whether an error count is less than or equal to a first threshold number of error bits and, in response to the error count being less than or equal to the first threshold number of error bits, performing correction of the error bits by the hardware logic implemented ECC engine associated with the node controller. The node controller is also configured to forward uncorrected data to a software logic implemented ECC engine, in response to the error count being greater than the first threshold number of error bits.

Abstract: Firmware is run in an emulated environment such that firmware is not embedded in its designed-for target device. Target device emulation software communicatively connects the firmware to the operating system in a manner so that communications sent from and received by the operating system are identical to communications that would be sent from and received by the operating system if the firmware were actually embedded in the target device instead of running in the emulated environment.

Abstract: A mechanism is provided for dynamic power and thermal capping in a flash storage system. A set of measurement values are received for the flash storage system, the set of measurement values comprising one or more of a set of current (I) measurement values, a set of voltage (V) measurement values, or a set of temperature (T) measurement values. An average current (Iavg) value from the set of current (I) measurements and, responsive to the average current (Iavg) value being greater than a predetermined maximum current (Imax) value, a determination is made as to whether a rate at which erase operations are performed for the flash storage system is greater than a predetermined minimum erase rate. Responsive to the rate at which erase operations are performed for the flash storage system being greater than the predetermined minimum erase rate, the rate at which erase operations are performed for the flash storage system are decreased by a predetermined value.

Abstract: Mechanisms are provided, in a Not AND (NAND) flash memory device, for providing hybrid error correction management. A NAND flash memory module and a node controller coupled to the NAND flash memory module are provided along with a hardware logic implemented error correction code (ECC) engine associated with the node controller. The node controller is configured to determine whether an error count is less than or equal to a first threshold number of error bits and, in response to the error count being less than or equal to the first threshold number of error bits, performing correction of the error bits by the hardware logic implemented ECC engine associated with the node controller. The node controller is also configured to forward uncorrected data to a software logic implemented ECC engine, in response to the error count being greater than the first threshold number of error bits.