Abstract: A converter unit configured to couple to a photovoltaic panel (PV) may include a controller to sense an output voltage and output current produced by the photovoltaic panel, and manage the output voltage of a corresponding power converter coupled to a DC bus to regulate the resultant bus voltage to a point that reduces overall system losses, and removes non-idealities when the panels are series connected. The controller may also adapt to output condition constraints, and perform a combination of input voltage and output voltage management and regulation, including maximum power point tracking (MPPT) for the PV. The output voltage and output current characteristic of the power converter may be shaped to present a power gradient—which may be hysteretically controlled—to the DC bus to compel an inverter coupled to the DC bus to perform its own MPPT to hold the DC-bus voltage within a determinate desired operating range.

Abstract: A converter unit configured to couple to a photovoltaic panel (PV) may include a controller to sense an input voltage and input current obtained from the photovoltaic panel, and manage the output voltage of a corresponding power converter coupled to a DC bus to regulate the resultant bus voltage to a point that reduces overall system losses, and removes non-idealities when the panels are series connected. The controller may also perform input voltage management and regulation, including maximum power point tracking (MPPT) for the PV. The controller may probe the bus voltage using a probe waveform generated according to a pseudo-random bit sequence (PRBS), to provide a probe signal that is distinct from the control steps performed by the controller. A PV array may feature a respective converter unit coupled to each PV, with each respective controller using a different and unique seed for generating its PRBS.

Abstract: A photovoltaic (PV) array system may include multiple PV strings, each PV string including respective PV panels coupled in series. Each PV string may be coupled in series with a first terminal of a respective string equalizer module. The string equalizer module may equalize a maximum power-point voltage (VMP) of the PV string before the PV strings combine to produce a single, composite DC bus voltage on a DC bus. To accomplish this, each string equalizer module may generate a respective adaptive string equalizer output voltage at its first terminal to tune a respective PV string voltage of its corresponding respective PV string to have the VMP of its corresponding PV string match respective VMP's of other PV strings. That is, PV strings may sink or source power from/to other PV strings, to equalize the VMP of each corresponding respective PV string.

Abstract: A converter unit configured to couple to a photovoltaic panel (PV) may include a controller to sense an output voltage and output current produced by the photovoltaic panel, and manage the output voltage of a corresponding power converter coupled to a DC bus to regulate the resultant bus voltage to a point that reduces overall system losses, and removes non-idealities when the panels are series connected. The controller may also adapt to output condition constraints, and perform a combination of input voltage and output voltage management and regulation, including maximum power point tracking (MPPT) for the PV. The output voltage and output current characteristic of the power converter may be shaped to present a power gradient—which may be hysteretically controlled—to the DC bus to compel an inverter coupled to the DC bus to perform its own MPPT to hold the DC-bus voltage within a determinate desired operating range.

Abstract: A converter unit configured to couple to a photovoltaic panel (PV) may include a controller to sense an input voltage and input current obtained from the photovoltaic panel, and manage the output voltage of a corresponding power converter coupled to a DC bus to regulate the resultant bus voltage to a point that reduces overall system losses, and removes non-idealities when the panels are series connected. The controller may also perform input voltage management and regulation, including maximum power point tracking (MPPT) for the PV. The controller may probe the bus voltage using a probe waveform generated according to a pseudo-random bit sequence (PRBS), to provide a probe signal that is distinct from the control steps performed by the controller. A PV array may feature a respective converter unit coupled to each PV, with each respective controller using a different and unique seed for generating its PRBS.

Abstract: A filter circuit, method of configuring the filter circuit, and a bit pump and transceiver employing the circuit and method. In one embodiment, the filter circuit includes a noise prediction equalizer that generates a noise prediction equalizer coefficient during activation of the bit pump to reduce an intersymbol interference associated with a receive signal propagating along a receive path of the bit pump. The filter circuit also includes a decision feedback equalizer that generates a decision feedback equalizer coefficient during the activation of the bit pump to reduce the intersymbol interference associated with the receive signal. The noise prediction equalizer is concatenated with the decision feedback equalizer during showtime of the bit pump to form a precoder associated with a transmit path of the bit pump.

Abstract: A signal detector for detecting the presence of a intermittent signal component in a signal. The signal detector receives each of the signal strength samples during a corresponding iteration, and compares a threshold value with the received signal sample. The signal detector sets a counter to a pre-determined number if the sample compared is greater than the threshold value. The signal detector decrements the persistence counter if a corresponding sample is not greater than the threshold value. If the persistence counter is greater than a trigger value, the detector indicates the presence of a intermittent signal component or otherwise declares the absence of a intermittent signal component. The detector may indicate the presence of a intermittent signal component by a logical value of 1 and the absence by a logical value of 0. The threshold value is composed of two components; the intermittent signal component and the background signal component.

Abstract: A double-talk detector for an echo canceller includes power estimators (60) and (62) which are utilized to measure the ERLE value in a calculator (64). This ERLE value is stored in a register (70) when it is the largest value generated. This register (70) is updated whenever a new and better ERLE occurs. A fraction of the value in register (70) is utilized as an input to a comparator (88), and then compared to the current ERLE value. If the current ERLE differs from the SERLE in register (70) an inhibit signal is generated for blocking the updates of an adaptive filter (40). The value stored in the register (70) is periodically decremented to reduce the value thereof. This decrement operation is performed in response to detection of an utterance from the far-end.

Abstract: A phase locked loop circuit generates an output clock that is in phase with a reference clock and is frequency jitter compensated at lower frequencies by translating intrinsic jitter frequency from low frequency to a predetermined range of higher frequencies. The phase locked loop circuit utilizes dithering circuitry to control a switched capacitor network in order to reduce the magnitude of the frequency jitter at lower frequencies. A phase detector and a loop filter of the phase locked loop circuit are implemented using digital circuitry. An oscillator of the phase locked loop is an analog oscillator which is digitally controlled and includes the switched capacitor network. Quantization error in the output clock is minimized by switching an LSB weighted capacitor in the oscillator at a frequency established by the dithering circuitry.

Abstract: A transient-error free interpolating decimator utilizes only two comb filters. The decimator has an integrator circuit, which receives a digitized signal at a first clock rate, and a differentiator circuit. The differentiator includes first and second comb filters for down converting the digital signal at the first clock rate to a second clock rate, and for providing sample points at first and second outputs; the differentiator circuit and the integrator circuit comprise a decimation filter. A delay circuit provides coarse sampling phase adjustments by delaying the second clock rate by a predetermined number of first-clock cycles. A counter generates the second clock rate and provides coarse sampling phase adjustments by adding or deleting cycles of the first clock to or form the second clock. A multiplexer circuit swaps the two outputs when necessary to prevent transient errors generated in the differentiators from being observed.

Abstract: A digital tone detector receives a modulated input signal selectively containing at least one tone signal component. Two demodulator circuits each demodulate the input signal wherein one demodulator circuit operates at the predetermined frequency of the tone and the other demodulator circuit operates at the second harmonic. When the input tone has a low spectral harmonic power, a ratio of the demodulated outputs of the two demodulators reliably detects the presence of the tone in the input signal.