Abstract: A circuit includes a source device coupled to an output circuit. The source device is configured to produce a sequence of digital values at a rate defined by a data period. The output circuit is configured to receive the sequence of digital values from the source device, generate a copy of each digital value at a predetermined point during the respective data period, and responsive to initiation of a data transaction during a given data period but before the predetermined point, output the digital value from the source device, whereas responsive to initiation of a data transaction during the given data period but after the predetermined point, output the copy of the digital value.

Abstract: Aspect of the present disclosure provide for a circuit. In an example, the circuit comprises a multiplexer having a first input, a second input, a control input, and an output. The circuit further comprises a first register having an input coupled to the output of the multiplexer and an output. The circuit further comprises a second register having an input coupled to the output of the first register and an output. The circuit further comprises a subtractor having a first input coupled to the output of the multiplexer and a second input coupled to the output of the second register. The circuit further comprises a third register having an input coupled to the output of the subtractor and an output coupled to the first input of the multiplexer.

Abstract: Aspect of the present disclosure provide for a circuit. In an example, the circuit comprises a multiplexer having a first input, a second input, a control input, and an output. The circuit further comprises a first register having an input coupled to the output of the multiplexer and an output. The circuit further comprises a second register having an input coupled to the output of the first register and an output. The circuit further comprises a subtractor having a first input coupled to the output of the multiplexer and a second input coupled to the output of the second register. The circuit further comprises a third register having an input coupled to the output of the subtractor and an output coupled to the first input of the multiplexer.

Abstract: Aspect of the present disclosure provide for a circuit. In an example, the circuit comprises a multiplexer having a first input, a second input, a control input, and an output. The circuit further comprises a first register having an input coupled to the output of the multiplexer and an output. The circuit further comprises a second register having an input coupled to the output of the first register and an output. The circuit further comprises a subtractor having a first input coupled to the output of the multiplexer and a second input coupled to the output of the second register. The circuit further comprises a third register having an input coupled to the output of the subtractor and an output coupled to the first input of the multiplexer.

Abstract: A clock signal generator (1) includes a phase locked loop (PLL) circuit (25) which requires a reference clock signal of at least a predetermined first frequency (fDIGCLK). A first clock signal (REFCLK) of a second frequency (fREF) that is substantially lower than the first frequency (fDIGCLK) is multiplied so as to produce a second clock signal (DIGCLK) which has a frequency at least as high as the first frequency (fDIGCLK) and which is phase-locked with respect to the first clock signal (REFCLK). The second clock signal (DIGCLK) is applied to a reference signal input of the PLL circuit (25), which produces an output clock signal (PLLCLK or CLKOUT).

Abstract: A clock signal generator (1) includes a phase locked loop (PLL) circuit (25) which requires a reference clock signal of at least a predetermined first frequency (fDIGCLK). A first clock signal (REFCLK) of a second frequency (fREF) that is substantially lower than the first frequency (fDIGCLK) is multiplied so as to produce a second clock signal (DIGCLK) which has a frequency at least as high as the first frequency (fDIGCLK) and which is phase-locked with respect to the first clock signal (REFCLK). The second clock signal (DIGCLK) is applied to a reference signal input of the PLL circuit (25), which produces an output clock signal (PLLCLK or CLKOUT).

Abstract: A sample rate converter suitable for use in an audio DAC includes a first estimating circuit (32A) generating first (TR) and second (STAMPR) signals synchronized to an asynchronous clock (MCLK) and representing the period and edge arrival times, respectively, of a reference clock (REFCLK). A second estimating circuit (32B) operates on the first and second signals to generate third (T1) and fourth (STAMP1) signals representing an input sample rate (32fsin) and arrival times of input data samples, respectively, which are applied to a coefficient and address generator (76) to generate read addresses and coefficients input to a FIFO memory (42) receiving digital input data at the input sample rate and a multiplication/accumulation circuit (78) receiving data from the FIFO memory. The multiplication/accumulation circuit produces an output signal (SRC-out) synchronized to the asynchronous clock at an output sample rate (32fsout).