Patents by Inventor Shawna M. Liff
Shawna M. Liff has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11605603Abstract: Embodiments may relate to a microelectronic package that includes a radio frequency (RF) chip coupled with a die by interconnects with a first pitch. The RF chip may further be coupled with a waveguide of a package substrate by interconnects with a second pitch that is different than the first pitch. The RF chip may facilitate conveyance of data to the waveguide as an electromagnetic signal with a frequency greater than approximately 20 gigahertz (GHz). Other embodiments may be described or claimed.Type: GrantFiled: April 29, 2019Date of Patent: March 14, 2023Assignee: Intel CorporationInventors: Adel A. Elsherbini, Georgios Dogiamis, Telesphor Kamgaing, Henning Braunisch, Johanna M. Swan, Shawna M. Liff, Aleksandar Aleksov
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Publication number: 20230074970Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first microelectronic component having a first direct bonding region, wherein the first direct bonding region includes first metal contacts and a first dielectric material between adjacent ones of the first metal contacts; a second microelectronic component having a second direct bonding region, wherein the second direct bonding region includes second metal contacts and a second dielectric material between adjacent ones of the second metal contacts, wherein the first microelectronic component is coupled to the second microelectronic component by interconnects, and wherein the interconnects include individual first metal contacts coupled to respective individual second metal contacts; and a void between an individual first metal contact that is not coupled to a respective individual second metal contact, wherein the void is in the first direct bonding region.Type: ApplicationFiled: November 9, 2022Publication date: March 9, 2023Applicant: Intel CorporationInventors: Adel A. Elsherbini, Veronica Aleman Strong, Shawna M. Liff, Brandon M. Rawlings, Jagat Shakya, Johanna M. Swan, David M. Craig, Jeremy Alan Streifer, Brennen Karl Mueller
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Publication number: 20230073026Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer, and including a first metallization stack at the first surface; a device layer on the first metallization stack; a second metallization stack on the device layer; and an interconnect on the first surface of the die electrically coupled to the first metallization stack; a conductive pillar in the first layer; and a second die, having a first surface and an opposing second surface, in a second layer on the first layer, wherein the first surface of the second die is coupled to the conductive pillar and to the second surface of the first die by a hybrid bonding region.Type: ApplicationFiled: September 9, 2021Publication date: March 9, 2023Applicant: Intel CorporationInventors: Adel A. Elsherbini, Kimin Jun, Shawna M. Liff, Johanna M. Swan, Han Wui Then
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Patent number: 11600594Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.Type: GrantFiled: March 30, 2022Date of Patent: March 7, 2023Assignee: Intel CorporationInventors: Shawna M. Liff, Adel A. Elsherbini, Johanna M. Swan, Arun Chandrasekhar
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Patent number: 11581282Abstract: In embodiments, a semiconductor package may include a first die and a second die. The package may additionally include a serializer/deserializer (SerDes) die coupled with the first and the second dies. The SerDes die may be configured to serialize signals transmitted from the first die to the second die, and deserialize signals received from the second die. Other embodiments may be described and/or claimed.Type: GrantFiled: August 30, 2018Date of Patent: February 14, 2023Assignee: Intel CorporationInventors: Adel A. Elsherbini, Johanna M. Swan, Shawna M. Liff, Gerald S. Pasdast
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Publication number: 20230018902Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.Type: ApplicationFiled: September 29, 2022Publication date: January 19, 2023Applicant: Intel CorporationInventors: Adel A. Elsherbini, Amr Elshazly, Arun Chandrasekhar, Shawna M. Liff, Johanna M. Swan
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Patent number: 11552035Abstract: An electronic package and method includes a substrate including a plurality of pads on a major surface. An electronic component including a plurality of pads on a major surface facing the major surface of the substrate. A stud bump electrically couples one of the plurality of pads of the substrate to one of the plurality of pads of the electronic component.Type: GrantFiled: August 3, 2021Date of Patent: January 10, 2023Assignee: Intel CorporationInventors: Zhaozhi Li, Sanka Ganesan, Debendra Mallik, Gregory Perry, Kuan H. Lu, Omkar Karhade, Shawna M. Liff
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Publication number: 20220415839Abstract: Embodiments disclosed herein include semiconductor dies with hybrid bonding layers and multi-die modules that are coupled together by hybrid bonding layers. In an embodiment, a semiconductor die comprises a die substrate, a pad layer over the die substrate, where the pad layer comprises first pads with a first dimension and a first pitch and second pads with a second dimension and a second pitch. In an embodiment, the semiconductor die further comprises a hybrid bonding layer over the pad layer. In an embodiment, the hybrid bonding layer comprises a dielectric layer, and an array of hybrid bonding pads in the dielectric layer, wherein the hybrid bonding pads comprise a third dimension and a third pitch.Type: ApplicationFiled: June 24, 2021Publication date: December 29, 2022Inventors: Aleksandar ALEKSOV, Feras EID, Johanna M. SWAN, Adel A. ELSHERBINI, Shawna M. LIFF
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Publication number: 20220415847Abstract: Embodiments disclosed herein include multi-die modules and methods of assembling multi-die modules. In an embodiment, a multi-die module comprises a first die. In an embodiment the first die comprises a first pedestal, a plateau around the first pedestal, and a stub extending up from the plateau. In an embodiment, the multi-die module further comprises a second die. In an embodiment, the second die comprises a second pedestal, where the second pedestal is attached to the first pedestal.Type: ApplicationFiled: June 24, 2021Publication date: December 29, 2022Inventors: Feras EID, Johanna M. SWAN, Shawna M. LIFF, Adel A. ELSHERBINI, Aleksandar ALEKSOV
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Publication number: 20220406701Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a first surface and an opposing second surface; and a chiplet having a first surface and an opposing second surface, wherein the chiplet is between the surface of the package substrate and the first surface of the die, wherein the first surface of the chiplet is coupled to the surface of the package substrate and the second surface of the chiplet is coupled to the first surface of the die, and wherein the chiplet includes: a capacitor at the first surface; and an element at the second surface, wherein the element includes a switching transistor or a diode.Type: ApplicationFiled: August 25, 2022Publication date: December 22, 2022Applicant: Intel CorporationInventors: Adel A. Elsherbini, Kaladhar Radhakrishnan, Krishna Bharath, Shawna M. Liff, Johanna M. Swan
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Publication number: 20220406751Abstract: A microelectronic assembly is provided, comprising: a first integrated circuit (IC) die at a first level, a second IC die at a second level, and a third IC die at a third level, the second level being in between the first level and the third level. A first interface between the first level and the second level is electrically coupled with high-density interconnects of a first pitch and a second interface between the second level and the third level is electrically coupled with interconnects of a second pitch. In some embodiments, at least one of the first IC die, second IC die, and third IC die comprises another microelectronic assembly. In other embodiments, at least one of the first IC die, second IC die, and third IC die comprises a semiconductor die.Type: ApplicationFiled: June 22, 2021Publication date: December 22, 2022Applicant: Intel CorporationInventors: Adel A. Elsherbini, Shawna M. Liff, Johanna M. Swan, Julien Sebot
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Publication number: 20220399277Abstract: An Integrated Circuit (IC), comprising a first conductive trace on a first die, a second conductive trace on a second die, and a conductive pathway electrically coupling the first conductive trace with the second conductive trace. The second die is coupled to the first die with interconnects. The conductive pathway comprises a portion of the interconnects located proximate to a periphery of a region in the first die through which the first conductive trace is not routable. In some embodiments, the conductive pathway reroutes electrical connections away from the region. The region comprises a high congestion zone having high routing density in some embodiments. In other embodiments, the region comprises a “keep-out” zone.Type: ApplicationFiled: June 11, 2021Publication date: December 15, 2022Applicant: INTEL CORPORATIONInventors: Adel A. Elsherbini, Scott E. Siers, Sathya Narasimman Tiagaraj, Gerald S. Pasdast, Zhiguo Qian, Kalyan C. Kolluru, Vivek Kumar Rajan, Shawna M. Liff, Johanna M. Swan
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Publication number: 20220399324Abstract: A die assembly comprising: a first component layer having conductive through-connections in an insulator, a second component layer comprising a die, and an active device layer (ADL) at an interface between the first component layer and the second component layer. The ADL comprises active elements electrically coupled to the first component layer and the second component layer. The die assembly further comprises a bonding layer electrically coupling the ADL to the second component layer. In some embodiments, the die assembly further comprises another ADL at another interface between the first component layer and a package support opposite to the interface. The first component layer may comprise another die having through-substrate vias (TSVs). The die and the another die may be fabricated using different process nodes.Type: ApplicationFiled: June 10, 2021Publication date: December 15, 2022Applicant: Intel CorporationInventors: Han Wui Then, Adel A. Elsherbini, Kimin Jun, Johanna M. Swan, Shawna M. Liff, Sathya Narasimman Tiagaraj, Gerald S. Pasdast, Aleksandar Aleksov, Feras Eid
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Publication number: 20220399305Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first microelectronic component, embedded in a first dielectric layer, including a surface and one or more side surfaces at least partially encapsulated by a first magnetic conductive material; and a second microelectronic component, embedded in a second dielectric layer on the first dielectric layer, including a surface and one or more side surfaces at least partially encapsulated by a second magnetic conductive material, wherein the second microelectronic component is coupled to the surface of the first microelectronic component by a hybrid bonding region, and wherein the second magnetic conductive material is coupled to the first magnetic conductive material.Type: ApplicationFiled: June 9, 2021Publication date: December 15, 2022Applicant: Intel CorporationInventors: Beomseok Choi, Adel A. Elsherbini, Han Wui Then, Johanna M. Swan, Shawna M. Liff
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Publication number: 20220399294Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a die-level interposer having a first surface and an opposing second surface; a first die coupled to the first surface of the die-level interposer by a first hybrid bonding region having a first pitch; a second die coupled to the second surface of the die-level interposer by a second hybrid bonding region having a second pitch different from the first pitch; and a third die coupled to the second surface of the die-level interposer by a third hybrid bonding region having a third pitch different from the first and second pitches.Type: ApplicationFiled: June 14, 2021Publication date: December 15, 2022Applicant: Intel CorporationInventors: Georgios Dogiamis, Qiang Yu, Adel A. Elsherbini, Shawna M. Liff
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Patent number: 11527501Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first microelectronic component having a first direct bonding region, wherein the first direct bonding region includes first metal contacts and a first dielectric material between adjacent ones of the first metal contacts; a second microelectronic component having a second direct bonding region and coupled to the first microelectronic component by the first and second direct bonding regions, wherein the second direct bonding region includes second metal contacts and a second dielectric material between adjacent ones of the second metal contacts, and wherein individual first metal contacts in the first direct bonding region are coupled to respective individual second metal contacts in the second direct bonding region; and a void between an individual first metal contact and a respective individual second metal contact.Type: GrantFiled: December 15, 2020Date of Patent: December 13, 2022Assignee: Intel CorporationInventors: Adel A. Elsherbini, Veronica Aleman Strong, Shawna M. Liff, Brandon M. Rawlings, Jagat Shakya, Johanna M. Swan, David M. Craig, Jeremy Alan Streifer, Brennen Karl Mueller
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Publication number: 20220384389Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.Type: ApplicationFiled: August 10, 2022Publication date: December 1, 2022Applicant: Intel CorporationInventors: Shawna M. Liff, Adel A. Elsherbini, Johanna M. Swan
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Patent number: 11508587Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; and a die embedded in the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts and the second conductive contacts are electrically coupled to conductive pathways in the package substrate.Type: GrantFiled: December 29, 2017Date of Patent: November 22, 2022Assignee: Intel CorporationInventors: Adel A. Elsherbini, Shawna M. Liff, Johanna M. Swan
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Patent number: 11508898Abstract: Piezoelectric devices are described fabricated in packaging buildup layers. In one example, a package has a plurality of conductive routing layers and a plurality of organic dielectric layers between the conductive routing layers. A die attach area has a plurality of vias to connect to a microelectronic die, the vias connecting to respective conductive routing layers. A piezoelectric device is formed on an organic dielectric layer, the piezoelectric device having at least one electrode coupled to a conductive routing layer.Type: GrantFiled: April 29, 2019Date of Patent: November 22, 2022Assignee: Intel CorporationInventors: Feras Eid, Shawna M. Liff
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Patent number: 11494682Abstract: Quantum computing assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a quantum computing assembly may include: a package substrate; a first die coupled to the package substrate; and a second die coupled to the second surface of the package substrate and coupled to the first die; wherein the first die or the second die includes quantum processing circuitry.Type: GrantFiled: December 29, 2017Date of Patent: November 8, 2022Assignee: Intel CorporationInventors: Adel A. Elsherbini, Shawna M. Liff, Jeanette M. Roberts, James S. Clarke