Patents by Inventor Shawna M. Liff
Shawna M. Liff has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250029892Abstract: Structures having a through-stack thermal sink for dual-sided devices are described. In an example, an integrated circuit structure includes a front side structure. The front side structure includes a device layer having a plurality of fin-based or nanowire-based transistors, and a plurality of metallization layers above the plurality of fin-based or nanowire-based transistors. A backside structure is below the plurality of fin-based or nanowire-based transistors. A carrier wafer or substrate is bonded to the front side structure. A thermal conductive via extends from a location at a bottom of or below the plurality of fin-based or nanowire-based transistors to a location on or into the carrier wafer or substrate.Type: ApplicationFiled: July 18, 2023Publication date: January 23, 2025Inventors: Conor P. PULS, Giorgio MARIOTTINI, Brenden ARRUDA, Shawna M. LIFF, Lei JIANG, Samson ODUNUGA, Gerardo MONTANO, Hannes GREVE, Apratim DHAR, Aaron M. WHITE
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Publication number: 20250022845Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a first die having a first surface and an opposing second surface embedded in a first dielectric layer, where the first surface of the first die is coupled to the second surface of the package substrate by first interconnects; a second die having a first surface and an opposing second surface embedded in a second dielectric layer, where the first surface of the second die is coupled to the second surface of the first die by second interconnects; and a third die having a first surface and an opposing second surface embedded in a third dielectric layer, where the first surface of the third die is coupled to the second surface of the second die by third interconnects.Type: ApplicationFiled: September 6, 2024Publication date: January 16, 2025Inventors: Adel A. Elsherbini, Feras Eid, Johanna M. Swan, Shawna M. Liff
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Patent number: 12199063Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.Type: GrantFiled: January 3, 2024Date of Patent: January 14, 2025Assignee: Intel CorporationInventors: Shawna M. Liff, Adel A. Elsherbini, Johanna M. Swan, Arun Chandrasekhar
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Patent number: 12199018Abstract: Disclosed herein are microelectronic assemblies including direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first subregion and a second subregion, and the first subregion has a greater metal density than the second subregion. In some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first metal contact and a second metal contact, the first metal contact has a larger area than the second metal contact, and the first metal contact is electrically coupled to a power/ground plane of the first microelectronic component.Type: GrantFiled: September 18, 2020Date of Patent: January 14, 2025Assignee: Intel CorporationInventors: Adel A. Elsherbini, Krishna Bharath, Han Wui Then, Kimin Jun, Aleksandar Aleksov, Mohammad Enamul Kabir, Shawna M. Liff, Johanna M. Swan, Feras Eid
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Patent number: 12199067Abstract: An embedded silicon bridge system including tall interconnect via pillars is part of a system in package device. The tall via pillars may span a Z-height distance to a subsequent bond pad from a bond pad that is part of an organic substrate that houses the embedded silicon bridge.Type: GrantFiled: April 5, 2021Date of Patent: January 14, 2025Assignee: Intel CorporationInventors: Adel A. Elsherbini, Henning Braunisch, Javier Soto Gonzalez, Shawna M. Liff
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Publication number: 20250015028Abstract: Disclosed herein are structures and techniques related to singulation of microelectronic components with direct bonding interfaces. For example, in some embodiments, a microelectronic component may include a surface, wherein conductive contacts are at the surface; a trench at a perimeter of the surface, the trench having a depth; and a burr in the trench having a height that is less than the depth of the trench.Type: ApplicationFiled: September 17, 2024Publication date: January 9, 2025Applicant: Intel CorporationInventors: Bhaskar Jyoti Krishnatreya, Nagatoshi Tsunoda, Shawna M. Liff, Sairam Agraharam
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Patent number: 12183961Abstract: A method of forming a waveguide comprises forming an elongate waveguide core including a dielectric material; and arranging a conductive sheet around an outside surface of the dielectric core to produce a conductive layer around the waveguide core.Type: GrantFiled: August 16, 2021Date of Patent: December 31, 2024Assignee: Intel CorporationInventors: Aleksandar Aleksov, Georgios C. Dogiamis, Telesphor Kamgaing, Sasha N. Oster, Adel A. Elsherbini, Shawna M. Liff, Johanna M. Swan, Brandon M. Rawlings, Richard J. Dischler
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Patent number: 12176323Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include: a first die having a first surface and an opposing second surface, first conductive contacts at the first surface of the first die, and second conductive contacts at the second surface of the first die; and a second die having a first surface and an opposing second surface, and first conductive contacts at the first surface of the second die; wherein the second conductive contacts of the first die are coupled to the first conductive contacts of the second die by interconnects, the second surface of the first die is between the first surface of the first die and the first surface of the second die, and a footprint of the first die is smaller than and contained within a footprint of the second die.Type: GrantFiled: April 25, 2022Date of Patent: December 24, 2024Assignee: Intel CorporationInventors: Adel A. Elsherbini, Henning Braunisch, Aleksandar Aleksov, Shawna M. Liff, Johanna M. Swan, Patrick Morrow, Kimin Jun, Brennen Mueller, Paul B. Fischer
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Patent number: 12165962Abstract: Disclosed herein are microelectronic assemblies including microelectronic components coupled by direct bonding, and related structures and techniques. In some embodiments, a microelectronic assembly may include a first microelectronic component including a first guard ring extending through at least a portion of a thickness of and along a perimeter; a second microelectronic component including a second guard ring extending through at least a portion of a thickness of and along a perimeter, where the first and second microelectronic components are coupled by direct bonding; and a seal ring formed by coupling the first guard ring to the second guard ring. In some embodiments, a microelectronic assembly may include a microelectronic component coupled to an interposer that includes a first liner material at a first surface; a second liner material at an opposing second surface; and a perimeter wall through the interposer and connected to the first and second liner materials.Type: GrantFiled: December 14, 2020Date of Patent: December 10, 2024Assignee: Intel CorporationInventors: Aleksandar Aleksov, Mohammad Enamul Kabir, Adel A. Elsherbini, Shawna M. Liff, Johanna M. Swan, Feras Eid
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Patent number: 12142510Abstract: Described herein are carrier assemblies, and related devices and methods. In some embodiments, a carrier assembly includes a carrier; a textured material including texturized microstructures coupled to the carrier; and microelectronic components mechanically coupled to the texturized microstructures. In some embodiments, a carrier assembly includes a carrier having a front side and a back side; an electrode on the front side of the carrier; a dielectric material on the electrode; a charging contact on the back side coupled to the electrode; and microelectronic components electrostatically coupled to the front side of the carrier. In some embodiments, a carrier assembly includes a carrier having a front side and a back side; electrodes on the front side; a dielectric material including texturized microstructures on the electrodes; charging contacts on the back side coupled to the plurality of electrodes; and microelectronic components mechanically and electrostatically coupled to the front side of the carrier.Type: GrantFiled: December 23, 2020Date of Patent: November 12, 2024Assignee: Intel CorporationInventors: Shawna M. Liff, Johanna M. Swan, Adel A. Elsherbini, Michael J. Baker, Aleksandar Aleksov, Feras Eid
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Publication number: 20240355750Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.Type: ApplicationFiled: June 28, 2024Publication date: October 24, 2024Inventors: Adel A. ELSHERBINI, Amr ELSHAZLY, Arun CHANDRASEKHAR, Shawna M. LIFF, Johanna M. SWAN
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Publication number: 20240355768Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor.Type: ApplicationFiled: July 2, 2024Publication date: October 24, 2024Applicant: Intel CorporationInventors: Adel A. Elsherbini, Krishna Bharath, Kevin P. O'Brien, Kimin Jun, Han Wui Then, Mohammad Enamul Kabir, Gerald S. Pasdast, Feras Eid, Aleksandar Aleksov, Johanna M. Swan, Shawna M. Liff
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Patent number: 12119317Abstract: Disclosed herein are structures and techniques related to singulation of microelectronic components with direct bonding interfaces. For example, in some embodiments, a microelectronic component may include: a surface, wherein conductive contacts are at the surface; a trench at a perimeter of the surface; and a burr in the trench.Type: GrantFiled: September 25, 2020Date of Patent: October 15, 2024Assignee: Intel CorporationInventors: Bhaskar Jyoti Krishnatreya, Nagatoshi Tsunoda, Shawna M. Liff, Sairam Agraharam
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Patent number: 12119291Abstract: Disclosed herein are microelectronic assemblies including microelectronic components coupled by direct bonding, and related structures and techniques. In some embodiments, a microelectronic assembly may include a first microelectronic component including a first guard ring extending through at least a portion of a thickness of and along a perimeter; a second microelectronic component including a second guard ring extending through at least a portion of a thickness of and along a perimeter, where the first and second microelectronic components are coupled by direct bonding; and a seal ring formed by coupling the first guard ring to the second guard ring. In some embodiments, a microelectronic assembly may include a microelectronic component coupled to an interposer that includes a first liner material at a first surface; a second liner material at an opposing second surface; and a perimeter wall through the interposer and connected to the first and second liner materials.Type: GrantFiled: December 14, 2020Date of Patent: October 15, 2024Assignee: Intel CorporationInventors: Aleksandar Aleksov, Mohammad Enamul Kabir, Adel A. Elsherbini, Shawna M. Liff, Johanna M. Swan, Feras Eid
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Publication number: 20240339410Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component, including an organic dielectric material; a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes metal contacts and a dielectric material between adjacent ones of the metal contacts, and wherein the dielectric material includes an inorganic dielectric material; and a third microelectronic component coupled to the first microelectronic component by wire bonding or solder.Type: ApplicationFiled: June 18, 2024Publication date: October 10, 2024Applicant: Intel CorporationInventors: Aleksandar Aleksov, Adel A. Elsherbini, Shawna M. Liff, Johanna M. Swan, Feras Eid, Randy B. Osborne, Van H. Le
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Patent number: 12113048Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a first die having a first surface and an opposing second surface embedded in a first dielectric layer, where the first surface of the first die is coupled to the second surface of the package substrate by first interconnects; a second die having a first surface and an opposing second surface embedded in a second dielectric layer, where the first surface of the second die is coupled to the second surface of the first die by second interconnects; and a third die having a first surface and an opposing second surface embedded in a third dielectric layer, where the first surface of the third die is coupled to the second surface of the second die by third interconnects.Type: GrantFiled: December 29, 2022Date of Patent: October 8, 2024Assignee: Intel CorporationInventors: Adel A. Elsherbini, Feras Eid, Johanna M. Swan, Shawna M. Liff
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Patent number: 12107060Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor.Type: GrantFiled: September 18, 2020Date of Patent: October 1, 2024Assignee: Intel CorproationInventors: Adel A. Elsherbini, Zhiguo Qian, Gerald S. Pasdast, Mohammad Enamul Kabir, Han Wui Then, Kimin Jun, Kevin P. O'Brien, Johanna M. Swan, Shawna M. Liff, Aleksandar Aleksov, Feras Eid
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Patent number: 12080652Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.Type: GrantFiled: June 29, 2023Date of Patent: September 3, 2024Assignee: Intel CorporationInventors: Adel A. Elsherbini, Amr Elshazly, Arun Chandrasekhar, Shawna M. Liff, Johanna M. Swan
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Publication number: 20240274576Abstract: Disclosed herein are microelectronic assemblies including direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region including metal contacts that are distributed non-uniformly. In some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first metal contact and a second metal contact, the first metal contact has a larger area than the second metal contact.Type: ApplicationFiled: April 11, 2024Publication date: August 15, 2024Applicant: Intel CorporationInventors: Feras Eid, Adel A. Elsherbini, Aleksandar Aleksov, Shawna M. Liff, Johanna M. Swan
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Patent number: 12062631Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor.Type: GrantFiled: September 18, 2020Date of Patent: August 13, 2024Assignee: Intel CorporationInventors: Adel A Elsherbini, Krishna Bharath, Kevin P. O'Brien, Kimin Jun, Han Wui Then, Mohammad Enamul Kabir, Gerald S. Pasdast, Feras Eid, Aleksandar Aleksov, Johanna M. Swan, Shawna M. Liff