Patents by Inventor Shay Aisman
Shay Aisman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240134731Abstract: A device includes a hardware block to perform a hardware process and internal logic coupled between a processing device, which executes instructions, and the hardware block. The internal logic can one of measure execution time or count clock cycles of at least a portion of the hardware process. The internal logic can further, in response to the measured execution time or the counted clock cycles satisfying a predetermined condition, provide data associated with the one of the execution time measurement or the clock cycles count to the processing device, the data being statistically indicative of a latency of data packets sent by the hardware process over a total time the hardware process executes.Type: ApplicationFiled: December 5, 2022Publication date: April 25, 2024Inventors: Natan Manevich, Dotan David Levi, Shay Aisman, Ariel Almog, Ran Avraham Koren
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Patent number: 11968089Abstract: A network device (ND) includes packet processing circuitry and performance optimization circuitry. The packet processing circuitry is connected to a network and is configured to process communication packets for communicating over the network. The packet processing circuitry includes a plurality of configuration registers for setting one or more operation parameters of the ND. The performance optimization circuitry is configured to improve a performance measure of the ND by iteratively calculating the performance measure and adjusting values of one or more of the configuration registers based on the performance measure.Type: GrantFiled: November 7, 2022Date of Patent: April 23, 2024Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Ido Gilboa, Shay Aisman, Sagi Arieli, Oren Vaserberger, Amit Mandelbaum, Doron Haritan Kazakov, Natali Shechtman, Iftah Levi, Amir Ancel
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Patent number: 11940933Abstract: A computing system includes at least one peripheral bus, a peripheral device connected to the at least one peripheral bus, at least one memory, and first and second system components. The first system component is (i) associated with a first address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The second system component is (i) associated with a second address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The first system component is arranged to cause the peripheral device to access the second address space that is associated with the second system component.Type: GrantFiled: March 2, 2021Date of Patent: March 26, 2024Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Idan Burstein, Dotan David Levi, Ariel Shahar, Lior Narkis, Igor Voks, Noam Bloch, Shay Aisman
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Patent number: 11916790Abstract: A network adapter includes a host interface, a network interface, a memory and packet processing circuitry. The memory holds a shared buffer and multiple queues allocated to the multiple host processors. The packet processing circuitry is configured to receive from the network interface data packets destined to the host processors, to store payloads of at least some of the data packets in the shared buffer, to distribute headers of at least some of the data packets to the queues, to serve the data packets to the host processors by applying scheduling among the queues, to detect congestion in the data packets destined to a given host processor among the host processors, and, in response to the detected congestion, to mitigate the congestion in the data packets destined to the given host processor, while retaining uninterrupted processing of the data packets destined to the other host processors.Type: GrantFiled: May 4, 2020Date of Patent: February 27, 2024Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Avi Urman, Lior Narkis, Noam Bloch, Eyal Srebro, Shay Aisman
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Patent number: 11899547Abstract: A computing apparatus includes a transaction-record memory and a comparator. The transaction-record memory is to receive and store one or more sequences of transaction records, each transaction record including a unique transaction ID and a transaction payload. The comparator is to compare the payloads of transaction records having the same transaction ID, and to initiate a responsive action in response to a discrepancy between the compared transaction payloads.Type: GrantFiled: November 30, 2021Date of Patent: February 13, 2024Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Sharon Ulman, Eyal Srebro, Shay Aisman
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Publication number: 20230359537Abstract: An apparatus includes operational circuitry and Hardware Diagnostics Circuitry (HDC). The HDC is configured to receive a definition of multiple trigger rules, each trigger rule specifying a respective trigger event as a function of trigger data sources in the operational circuitry, to receive a definition of (i) a pre-trigger logging set selected from among a plurality of diagnostics data sources in the operational circuitry, and (ii) for each trigger rule, a respective post-trigger logging set including a set of one or more of the diagnostics data sources, and, during operation of the operational circuitry, to log the diagnostics data sources in the pre-trigger logging set, to log the trigger data sources and to repeatedly evaluate the trigger rules, and, in response to triggering of a given trigger event by a given trigger rule, to start logging the diagnostics data sources in the post-trigger logging set of the given trigger rule.Type: ApplicationFiled: July 6, 2023Publication date: November 9, 2023Inventors: Ran Koren, Shay Aisman, Itamar Rabenstein, Amir Ancel
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Patent number: 11740985Abstract: An apparatus includes operational circuitry and Hardware Diagnostics Circuitry (HDC). The HDC is configured to receive a definition of multiple trigger rules, each trigger rule specifying a respective trigger event as a function of trigger data sources in the operational circuitry, to receive a definition of (i) a pre-trigger logging set selected from among a plurality of diagnostics data sources in the operational circuitry, and (ii) for each trigger rule, a respective post-trigger logging set including a set of one or more of the diagnostics data sources, and, during operation of the operational circuitry, to log the diagnostics data sources in the pre-trigger logging set, to log the trigger data sources and to repeatedly evaluate the trigger rules, and, in response to triggering of a given trigger event by a given trigger rule, to start logging the diagnostics data sources in the post-trigger logging set of the given trigger rule.Type: GrantFiled: April 27, 2021Date of Patent: August 29, 2023Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Ran Koren, Shay Aisman, Itamar Rabenstein, Amir Ancel
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Patent number: 11711320Abstract: In one embodiment, a network device, including packet processing circuitry, which includes at least one interface configured to receive packets, and packet forwarding circuitry configured to make respective forwarding decisions for respective ones of the packets, wherein the packet processing circuitry is configured to assign sequence numbers to the packets in at least one stage of packet processing, find missing packets in at least one corresponding later stage of the packet processing responsively to checking for missing sequence numbers among the assigned sequence numbers, and report the missing packets.Type: GrantFiled: July 12, 2021Date of Patent: July 25, 2023Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Sharon Ulman, Eyal Srebro, Shay Aisman
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Publication number: 20230168978Abstract: A computing apparatus includes a transaction-record memory and a comparator. The transaction-record memory is to receive and store one or more sequences of transaction records, each transaction record including a unique transaction ID and a transaction payload. The comparator is to compare the payloads of transaction records having the same transaction ID, and to initiate a responsive action in response to a discrepancy between the compared transaction payloads.Type: ApplicationFiled: November 30, 2021Publication date: June 1, 2023Inventors: Sharon Ulman, Eyal Srebro, Shay Aisman
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Publication number: 20230054873Abstract: A network device (ND) includes packet processing circuitry and performance optimization circuitry. The packet processing circuitry is connected to a network and is configured to process communication packets for communicating over the network. The packet processing circuitry includes a plurality of configuration registers for setting one or more operation parameters of the ND. The performance optimization circuitry is configured to improve a performance measure of the ND by iteratively calculating the performance measure and adjusting values of one or more of the configuration registers based on the performance measure.Type: ApplicationFiled: November 7, 2022Publication date: February 23, 2023Inventors: Ido Gilboa, Shay Aisman, Sagi Arieli, Oren Vaserberger, Amit Mandelbaum, Doron Haritan Kazakov, Natali Shechtman, Iftah Levi, Amir Ancel
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Publication number: 20230008730Abstract: In one embodiment, a network device, including packet processing circuitry, which includes at least one interface configured to receive packets, and packet forwarding circuitry configured to make respective forwarding decisions for respective ones of the packets, wherein the packet processing circuitry is configured to assign sequence numbers to the packets in at least one stage of packet processing, find missing packets in at least one corresponding later stage of the packet processing responsively to checking for missing sequence numbers among the assigned sequence numbers, and report the missing packets.Type: ApplicationFiled: July 12, 2021Publication date: January 12, 2023Inventors: Sharon Ulman, Eyal Srebro, Shay Aisman
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Patent number: 11546216Abstract: A network device (ND) includes packet processing circuitry and performance optimization circuitry. The packet processing circuitry is connected to a network and is configured to process communication packets for communicating over the network. The packet processing circuitry includes a plurality of configuration registers for setting one or more operation parameters of the ND. The performance optimization circuitry is configured to improve a performance measure of the ND by iteratively calculating the performance measure and adjusting values of one or more of the configuration registers based on the performance measure.Type: GrantFiled: December 22, 2020Date of Patent: January 3, 2023Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Ido Gilboa, Shay Aisman, Sagi Arieli, Oren Vaserberger, Amit Mandelbaum, Doron Haritan Kazakov, Natali Shechtman, Iftah Levi, Amir Ancel
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Publication number: 20220334939Abstract: An apparatus includes operational circuitry and Hardware Diagnostics Circuitry (HDC). The HDC is configured to receive a definition of multiple trigger rules, each trigger rule specifying a respective trigger event as a function of trigger data sources in the operational circuitry, to receive a definition of (i) a pre-trigger logging set selected from among a plurality of diagnostics data sources in the operational circuitry, and (ii) for each trigger rule, a respective post-trigger logging set including a set of one or more of the diagnostics data sources, and, during operation of the operational circuitry, to log the diagnostics data sources in the pre-trigger logging set, to log the trigger data sources and to repeatedly evaluate the trigger rules, and, in response to triggering of a given trigger event by a given trigger rule, to start logging the diagnostics data sources in the post-trigger logging set of the given trigger rule.Type: ApplicationFiled: April 27, 2021Publication date: October 20, 2022Inventors: Ran Koren, Shay Aisman, Itamar Rabenstein, Amir Ancel
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Publication number: 20220283964Abstract: A computing system includes at least one peripheral bus, a peripheral device connected to the at least one peripheral bus, at least one memory, and first and second system components. The first system component is (i) associated with a first address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The second system component is (i) associated with a second address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The first system component is arranged to cause the peripheral device to access the second address space that is associated with the second system component.Type: ApplicationFiled: March 2, 2021Publication date: September 8, 2022Inventors: Idan Burstein, Dotan David Levi, Ariel Shahar, Lior Narkis, Igor Voks, Noam Bloch, Shay Aisman
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Publication number: 20220200859Abstract: A network device (ND) includes packet processing circuitry and performance optimization circuitry. The packet processing circuitry is connected to a network and is configured to process communication packets for communicating over the network. The packet processing circuitry includes a plurality of configuration registers for setting one or more operation parameters of the ND. The performance optimization circuitry is configured to improve a performance measure of the ND by iteratively calculating the performance measure and adjusting values of one or more of the configuration registers based on the performance measure.Type: ApplicationFiled: December 22, 2020Publication date: June 23, 2022Inventors: Ido Gilboa, Shay Aisman, Sagi Arieli, Oren Vaserberger, Amit Mandelbaum, Doron Haritan Kazakov, Natali Shechtman, Iftah Levi, Amir Ancel
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Publication number: 20210344600Abstract: A network adapter includes a host interface, a network interface, a memory and packet processing circuitry. The memory holds a shared buffer and multiple queues allocated to the multiple host processors. The packet processing circuitry is configured to receive from the network interface data packets destined to the host processors, to store payloads of at least some of the data packets in the shared buffer, to distribute headers of at least some of the data packets to the queues, to serve the data packets to the host processors by applying scheduling among the queues, to detect congestion in the data packets destined to a given host processor among the host processors, and, in response to the detected congestion, to mitigate the congestion in the data packets destined to the given host processor, while retaining uninterrupted processing of the data packets destined to the other host processors.Type: ApplicationFiled: May 4, 2020Publication date: November 4, 2021Inventors: Avi Urman, Lior Narkis, Noam Bloch, Eyal Srebro, Shay Aisman