Abstract: A single-exposure high dynamic range (HDR) image sensor utilizes a charge amplifier having a selectively coupled conversion capacitor to read a single photodiode charge during a multi-phase readout operation. An overflow readout is performed during the photodiode charge integration phase, and utilizes the conversion capacitor to read overflow signals indicating rapidly rising photodiode charges caused by extreme exposure conditions, which also prevents saturation of the photodiode. At the end of the integration phase, the remaining photodiode charge is then measured using two readouts: a high sensitivity readout during which the storage capacitor de-coupled to accurately measure low-light conditions, and a low sensitivity readout during which the remaining photodiode charge is stored on the storage capacitor to provide normal light image data. Final single exposure HDR image data is then calculated by summing the overflow image data with the high-sensitivity and/or the low-sensitivity image data.

Abstract: An endoscope system includes a host device and an endoscope including a very small area CMOS image sensor having only four pads (power, ground, digital in, analog out), and including an array of 4T pixels and associated control circuitry for performing correlated double sampling (CDS) to generate analog reset level and analog signal level values associated with light detected by photodiodes in each pixel. Instead of processing the analog values on-chip, the analog reset values and analog signal values are transmitted in separate sets one row at a time along with interleaved synchronization signals by way of a single analog contact pad to the host device of the endoscopic system, which uses the synchronization signals to reconstruct the sensor's internal clock in order to process the analog values. The endoscope housing thus requires only four wires and is made very small.

Abstract: A single-exposure high dynamic range (HDR) image sensor utilizes a charge amplifier having a selectively coupled conversion capacitor to read a single photodiode charge during a multi-phase readout operation. An overflow readout is performed during the photodiode charge integration phase, and utilizes the conversion capacitor to read overflow signals indicating rapidly rising photodiode charges caused by extreme exposure conditions, which also prevents saturation of the photodiode. At the end of the integration phase, the remaining photodiode charge is then measured using two readouts: a high sensitivity readout during which the storage capacitor de-coupled to accurately measure low-light conditions, and a low sensitivity readout during which the remaining photodiode charge is stored on the storage capacitor to provide normal light image data. Final single exposure HDR image data is then calculated by summing the overflow image data with the high-sensitivity and/or the low-sensitivity image data.

Abstract: A single-exposure high dynamic range (HDR) image sensor utilizes a charge amplifier having two different charge-to-voltage conversion capacitors that read a single photodiode charge during a two-phase readout operation. The first capacitor has a lower capacitance and therefore higher conversion gain (sensitivity), and the second capacitor has a higher capacitance and therefore lower conversion gain (sensitivity). The two-phase readout operation samples the photodiode charge twice, once using the high sensitivity capacitor and once using the low sensitivity capacitor. The high sensitivity readout phase provides detailed low light condition data but is saturated under brighter light conditions, and the low sensitivity readout phase provides weak data under low light conditions but provides high quality image data under brighter light conditions. The final HDR image is created by combining both high and low sensitivity images into a single image while giving each of them the correct weighted value.

Abstract: A single-exposure high dynamic range (HDR) image sensor utilizes a charge amplifier having two different charge-to-voltage conversion capacitors that read a single photodiode charge during a two-phase readout operation. The first capacitor has a lower capacitance and therefore higher conversion gain (sensitivity), and the second capacitor has a higher capacitance and therefore lower conversion gain (sensitivity). The two-phase readout operation samples the photodiode charge twice, once using the high sensitivity capacitor and once using the low sensitivity capacitor. The high sensitivity readout phase provides detailed low light condition data but is saturated under brighter light conditions, and the low sensitivity readout phase provides weak data under low light conditions but provides high quality image data under brighter light conditions. The final HDR image is created by combining both high and low sensitivity images into a single image while giving each of them the correct weighted value.

Abstract: A very small area CMOS image sensor, e.g., for an endoscopic system, includes only four pads (power, ground, digital in, analog out), and includes an array of 4T pixels and associated control circuitry for performing correlated double sampling (CDS) to generate analog reset level and analog signal level values associated with light detected by photodiodes in each pixel. Instead of processing the analog values on-chip, the analog reset values and analog signal values are transmitted in separate sets one row at a time along with interleaved synchronization signals by way of a single analog contact pad, e.g., to a host device of an endoscopic system, which uses the synchronization signals to reconstruct the sensor's internal clock in order to process the analog values. An endoscope housing incorporating the CMOS image sensor thus requires only four wires.

Abstract: A very small area CMOS image sensor, e.g., for an endoscopic system, includes only four pads (power, ground, digital in, analog out), and includes an array of 4T pixels and associated control circuitry for performing correlated double sampling (CDS) to generate analog reset level and analog signal level values associated with light detected by photodiodes in each pixel. Instead of processing the analog values on-chip, the analog reset values and analog signal values are transmitted in separate sets one row at a time along with interleaved synchronization signals by way of a single analog contact pad, e.g., to a host device of an endoscopic system, which uses the synchronization signals to reconstruct the sensor's internal clock in order to process the analog values. An endoscope housing incorporating the CMOS image sensor thus requires only four wires.

Abstract: A large image sensor structure is created by tiling a plurality of image sensor dies, wherein each of the image sensor dies includes a pixel array that extends to three edges of the die, and control circuitry located along a fourth edge of the die. None of the control circuitry required to access the pixel array (e.g., none of the row driver circuitry) is located in the pixel array, thereby enabling consistent spacing of pixels across the pixel array. Because the pixel array of each image sensor die extends to three edges of the die, the pixel array of each image sensor die can abut up to three pixel arrays in other image sensor dies to form a large image sensor structure having 2×N tiled image sensor dies.

Abstract: A large image sensor structure is created by tiling a plurality of image sensor dies, wherein each of the image sensor dies includes a pixel array that extends to three edges of the die, and control circuitry located along a fourth edge of the die. None of the control circuitry required to access the pixel array (e.g., none of the row driver circuitry) is located in the pixel array, thereby enabling consistent spacing of pixels across the pixel array. Because the pixel array of each image sensor die extends to three edges of the die, the pixel array of each image sensor die can abut up to three pixel arrays in other image sensor dies to form a large image sensor structure having 2×N tiled image sensor dies.

Abstract: An imaging system including column-parallel ADCs that operate in response to a single slope global ramp signal and a matched global ramp line signal that has a voltage representative of a dark pixel value. The signal paths of the global ramp signal and the matched global ramp line signal are matched to minimize noise effects. Prior to performing a pixel read operation, the global ramp signal is increased through a first voltage range (below the dark pixel value) to ensure that the column-parallel ADCs are operating in a linear range. The first voltage range can be adjusted to cancel offset error associated with the column parallel ADCs. The column-parallel ADCs provide output signals having a full voltage swing between VDD and ground.

Abstract: An imaging system including column-parallel ADCs that operate in response to a single slope global ramp signal and a matched global ramp line signal that has a voltage representative of a dark pixel value. The signal paths of the global ramp signal and the matched global ramp line signal are matched to minimize noise effects. Prior to performing a pixel read operation, the global ramp signal is increased through a first voltage range (below the dark pixel value) to ensure that the column-parallel ADCs are operating in a linear range. The first voltage range can be adjusted to cancel offset error associated with the column parallel ADCs. The column-parallel ADCs provide output signals having a full voltage swing between VDD and ground.