Abstract: Systems and methods for dynamic and adaptive interrupt coalescing are disclosed. NVM Express (NVMe) implements a paired submission queue and completion queue mechanism, with host software on the host device placing commands into the submission queue. The memory device notifies the host device, via an interrupt, of entries on the completion queue. Responsive to receiving the interrupt, the host device access the completion queue to access entries placed by the memory device therein. The host device may take a certain amount of time to service the interrupt resulting in host latency. Given knowledge of the host latency, the memory device time the sending of the interrupt so that, given the host latency, the memory device may post the entry to the completion queue in a timely manner.

Abstract: The present disclosure generally relates to a method and device for simultaneously decoding data. Rather than sending data to be decoded to a single decoder, the data can be sent to multiple, available decoders so that the data can be decode in parallel. The data decoded from the first decoder that completes decoding of the data will be delivered to the host device. All remaining decoded data that was decoded in parallel will be discarded. The decoders operating simultaneously in parallel can operate using different parameters such as different calculation precision (power levels). By utilizing multiple decoders simultaneously in parallel, the full functionality of the data storage device's decoding capabilities are utilized without increasing latency.

Abstract: A method and apparatus for operating a solid state drive is disclosed comprising receiving at least two commands from a host requiring an action by the solid state drive in a preliminary order, ordering the at least two commands based upon a quality of service classification for the at least two commands to a final order and executing the at least two commands on the solid state drive in the final order, wherein an operational parameter of the solid state drive is modified by at least one of the at least two commands.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to set a decoder in data mode, read host memory buffer data and hashes from a host memory buffer, generate a first calculated hash, set the decoder in hash mode, generate a second calculated hash, and determine whether the second calculated hash is the same as a root hash. The controller is further configured to set an encoder in data mode, generate a first new hash, write new data and the first new hash to a host memory buffer, set the encoder to hash mode, calculate a second new hash, and update a root hash with the second new hash.

Abstract: A method and system for cache-based flow of a simple copy command is disclosed. The present disclosure generally relates to methods and systems for executing a simple copy command in a manner that mitigates additional latency in the device. According to certain embodiments, a copy command manager that includes one or more copy command slots is provided. When a simple copy command is received from a host, a copy command slot is allocated to the command, and the simple copy command is copied into the copy command slot. Upon copying the simple copy command to the copy command slot, an overlap table of the data storage device controller is updated to indicate the copy has been completed, and the completion is posted to the host. After posting, the simple copy command is carried out in the background through completion.

Abstract: A method and apparatus for operating a solid state drive is disclosed comprising receiving at least two commands from a host requiring an action by the solid state drive in a preliminary order, ordering the at least two commands based upon a quality of service classification for the at least two commands to a final order and executing the at least two commands on the solid state drive in the final order, wherein an operational parameter of the solid state drive is modified by at least one of the at least two commands.

Abstract: Embodiments of the present disclosure generally relate to a target device handling overlap write commands. In one embodiment, a target device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes a random accumulated buffer, a sequential accumulated buffer, and an overlap accumulated buffer. The controller is configured to receive a new write command, classify the new write command, and write data associated with the new write command to one of the random accumulated buffer, the sequential accumulated buffer, or the overlap accumulated buffer. Once the overlap accumulated buffer becomes available, the controller first flushes to the non-volatile memory the data in the random accumulated buffer and the sequential accumulated buffer that was received prior in sequence to the data in the overlap accumulated buffer. The controller then flushes the available overlap accumulated buffer, ensuring that new write commands override prior write commands.

Abstract: A method and apparatus for enforcing privacy within one or more memories of a data storage system are disclosed. In one embodiment, sensor data containing personally identifiable information (PII) is provided to a memory. In some embodiments, the memory of disclosed systems and methods may be volatile, non-volatile, or a combination. Within the memory, PII is detected in some embodiments by AI-based computer vision, voice recognition, or natural language processing methods. Detected PII is obfuscated within the memory prior to making the sensor data available to other systems or memories. In some embodiments, once PII has been obfuscated, the original sensor data is overwritten, deleted, or otherwise made unavailable.

Abstract: A data storage device includes a memory device, an always on (AON) application specific integrated circuit (ASIC), and a controller coupled to the memory device and the AON ASIC. When the data storage device enters a low power state, the controller generates and stores security data associated with context data in a power management integrated circuit (PMIC). The context data is stored in both the memory device and a host memory buffer (HMB). A location of the context data in the HMB is stored in the PMIC with the security data. When the data storage device exits the low power state, the address stored in the PMIC is utilized to retrieve the context data from the HMB. The retrieved context data is verified against the security data by the controller.

Abstract: A storage system has two submission queue doorbell registers associated with a submission queue in a host. The storage system fetches and executes a command from the submission queue only in response to both submission queue doorbell registers being written. The second submission queue doorbell register may be visible (and directly written to) by the host or invisible (and indirectly written to) by the host. The use of two submission queue doorbell registers for a single submission queue can be used as a protection mechanism to protect an administration command submission queue of a child controller in a multiple physical function Non-Volatile Memory Express (NVMe) device (MFND).

Abstract: An arrangement is described used to throttle data in a connected computer device having a device configured to transmit and receive data from a host, the device comprising, a device controller configured to interact with at least memory array and a data transfer throttling arrangement, the data transfer throttling arrangement configured to measure a bandwidth threshold for the device controller and pass data through the device controller when a bandwidth of the device controller is one of at and below a threshold.

Abstract: The disclosure relates in some aspects to managing the fetching and execution of commands stored in submission queues. For example, execution of a command may be blocked at a data storage apparatus due to an internal blocking condition (e.g., a large number of commands of a particular type are pending for execution at the data storage device). As another example, execution of a command may be blocked at a data storage apparatus due to an external blocking condition (e.g., a host device may specify that certain commands are to be executed immediately one after another). The disclosure relates in some aspects to controlling how commands are fetched and executed so that commands that cannot be executed by the data storage apparatus in the near future do not prevent other commands (that are not subject to the same blocking condition) from being executed.

Abstract: A storage system has two submission queue doorbell registers associated with a submission queue in a host. The storage system fetches and executes a command from the submission queue only in response to both submission queue doorbell registers being written. The second submission queue doorbell register may be visible (and directly written to) by the host or invisible (and indirectly written to) by the host. The use of two submission queue doorbell registers for a single submission queue can be used as a protection mechanism to protect an administration command submission queue of a child controller in a multiple physical function Non-Volatile Memory Express (NVMe) device (MFND).

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive new debug information, determine that a debug buffer does not have any available free entries for the new debug information, compare the priority information to a lowest priority information of old debug information stored in the debug buffer, remove a most recent old debug information that has a lowest priority information from the debug buffer, and place the new debug information and corresponding priority information in the debug buffer.

Abstract: A data storage device and method for securely storing and retrieving data at a data storage device. The disclosure includes a reverse encryption where a decryption function is applied to plaintext data to generate ciphertext data. Conversely, the disclosure includes applying an encryption function to ciphertext data to generate plaintext data. This involves using an encryption function that is inverse, and symmetric, to the decryption function. In some specific examples, this includes sharing cryptography engines for securing user data in a storage medium and securing device management data in host memory.

Abstract: In the context of data storage, an approach to pre-fetching data prior to a read request involves receiving a read request and a next read request, and updating metadata corresponding to the read request with a next data storage address corresponding to the next read request. Responsive to again receiving the read request at a later time, the next data storage address can be read from the read request metadata and the next data can be pre-fetched from the next data storage address in advance of processing a following read request. Furthermore, the next data can be pre-fetched during read queue idle time and stored in a cache buffer, in anticipation of another incoming next read request, responsive to which the next data can be returned to the host from the buffer rather than from a read of non-volatile memory.

Abstract: A circuit debug apparatus for debugging an integrated circuit that causes a functional fault may include a processor configured to extract a scan pattern of a scan chain of the integrated circuit while the integrated circuit is in a scan mode. The scan pattern includes a plurality of logic states for a corresponding plurality of logic circuits of the integrated circuit. The processor may also be configured to apply a modified scan pattern to the integrated circuit while the integrated circuit is in the scan mode, where the modified scan pattern includes a test pattern configured to eliminate the functional fault. The processor may be further configured to determine whether the integrated circuit with the modified scan pattern produces the functional fault while the integrated circuit is in a functional mode.

Abstract: A data storage device includes a memory device and a controller. The controller is configured to receive host commands, such as write commands. Upon determining that a received plurality of write commands are sequential, but includes one or more write commands that are unaligned with a memory granularity of the memory device, the one or more write commands are revised such that the one or more write commands are aligned with the memory granularity. The revised write command includes a first of the one or more write commands and a portion of a second of the one or more write commands. A beginning of the revised write command is aligned with the memory granularity and the end of the revised write command is also aligned with the memory granularity.

Abstract: A storage device includes a controller that can dynamically adjust the zone active limit (ZAL) for a zoned namespace (ZNS). Rather than assuming a worst-case scenario for the ZNS, the ZAL can be dynamically adjusted, even after providing the ZAL to a host device. In so doing, device behavior changes due to factors such as temperature, failed or flipped bit count, and device cycling can be considered as impacting the ZAL. The ZAL can then be adjusted over time, and the new ZAL can be communicated to the host device. As such, rather than a fixed, worst-case ZAL, the host device will receive updated ZAL values over time as the device performs.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a command, wherein the command comprises a plurality of logical block addresses (LBAs), determine that one or more LBAs of the plurality of LBAs are not aligned to a transfer layer packet (TLP) boundary, determine whether the one or more LBAs that are not aligned to a TLP boundary has a head that is unaligned that matches a previously stored tail that is unaligned, and merge and transfer the head that is unaligned with a previously stored tail that is unaligned when the head that is unaligned matches the previously stored tail that is unaligned.