Abstract: A memory system includes a memory device including an array of storage transistors for storing data where the storage transistors are organized in multiple memory banks, each memory bank including multiple memory pages; and a control circuit configured to interact with the memory device to perform read and write operations. The control circuit includes a read queue configured to store active read requests for reading data from the memory device, a write queue configured to store active write requests for writing data to the memory device, and a write staging buffer configured to store pending write requests received by the control circuit and to transfer the pending write requests to the write queue to maximize the number of active write requests that are addressed to different memory banks of the memory device.

Abstract: A memory system includes a memory device including an array of storage transistors organized in multiple memory banks, each memory bank including multiple memory pages; and a control circuit configured to interact with the memory device to perform read and write operations. The control circuit includes a read queue configured to store active read requests for reading data from the memory device, a write queue configured to store active write requests for writing data to the memory device, a command selector to select one or more commands issued by the read queue or the write queue, and a virtual to physical address translator to convert the memory address of the selected command encoded with the virtual bank index to a corresponding memory physical addresses, the selected command with the memory physical address being issued to the memory device for execution at the memory device.

Abstract: A memory device includes: (a) one or more memory circuits having physical memory pages identified by physical page addresses, each physical memory page being provided to store a memory page; and (b) a control circuit configured for managing read or write operations in each memory circuit. The control circuit manages both a wear-leveling scheme and read and write operations in the memory circuits.

Abstract: A memory system including a memory device of storage transistors organized in multiple memory banks where the memory device interacts with a controller device to perform read and write operations. In some embodiments, the controller device is configured to issue to the memory device a write command and a write termination command, where the write command causing the memory device to initiate a write operation in the memory device and the write termination command causing the memory device to terminate the write operation. In one embodiment, the controller device issues a write abort command as the write termination command to terminate a write operation in progress at a certain memory bank of the memory device in order to issue a read command to read data from the same memory bank. The terminated write operation can resume after the completion of the read operation.

Abstract: In some embodiments, a memory device implements a tile-based architecture including an arrangement of independently and concurrently operable arrays or tiles of memory transistors where each tile includes memory transistors that are arranged in a three-dimensional array and a localized modular control circuit operating the memory transistors in the tile. The tile-based architecture of the memory device enables concurrent memory access to multiple tiles, which enables independent and concurrent memory operations to be carried out across multiple tiles. The tile-based concurrent access to the memory device has the benefits of increasing the memory bandwidth and lowering the tail latency of the memory device by ensuring high availability of storage transistors.

Abstract: Embodiments are generally directed to performance of additional refresh operations during self-refresh mode. An embodiment of a memory device includes one or more memory banks, a mode register set, the mode register set including a first set of mode register bits, and a control logic to provide control operations for the memory device, the operations including refresh operations for the one or more memory banks in a refresh credit mode. The control logic is to perform one or more extra refresh cycles in response to receipt of a self-refresh command, the self-refresh command to provide current refresh status information, and is to store information in the first set of mode register bits regarding a modified refresh status after the performance of the one or more extra refresh cycles.

Abstract: Embodiments are generally directed to performance of additional refresh operations during self-refresh mode. An embodiment of a memory device includes one or more memory banks, a mode register set, the mode register set including a first set of mode register bits, and a control logic to provide control operations for the memory device, the operations including refresh operations for the one or more memory banks in a refresh credit mode. The control logic is to perform one or more extra refresh cycles in response to receipt of a self-refresh command, the self-refresh command to provide current refresh status information, and is to store information in the first set of mode register bits regarding a modified refresh status after the performance of the one or more extra refresh cycles.

Abstract: Embodiments are generally directed to performance of additional refresh operations during self-refresh mode. An embodiment of a memory device includes one or more memory banks, a mode register set, the mode register set including a first set of mode register bits, and a control logic to provide control operations for the memory device, the operations including refresh operations for the one or more memory banks in a refresh credit mode. The control logic is to perform one or more extra refresh cycles in response to receipt of a self-refresh command, the self-refresh command to provide current refresh status information, and is to store information in the first set of mode register bits regarding a modified refresh status after the performance of the one or more extra refresh cycles.

Abstract: Embodiments are generally directed to performance of additional refresh operations during self-refresh mode. An embodiment of a memory device includes one or more memory banks, a mode register set, the mode register set including a first set of mode register bits, and a control logic to provide control operations for the memory device, the operations including refresh operations for the one or more memory banks in a refresh credit mode. The control logic is to perform one or more extra refresh cycles in response to receipt of a self-refresh command, the self-refresh command to provide current refresh status information, and is to store information in the first set of mode register bits regarding a modified refresh status after the performance of the one or more extra refresh cycles.