Patents by Inventor Shay-Jan Huang

Shay-Jan Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6430529
    Abstract: The invention comprises an efficient system and method for performing the modified discrete cosine transform (MDCT) in support of time-domain aliasing cancellation (TDAC) perceptive encoding compression of digital audio. In one embodiment, an AC-3 encoder performs a required time-domain to frequency-domain transformation via a MDCT. The AC-3 specification presents a non-optimized equation for calculating the MDCT. In one embodiment of the present invention, an MDCT transformer is utilized which produces the same results as carrying out the calculations directly as in the AC-3 equation, but requires substantially lower computational resources. Because the TDAC scheme requires MDCT calculations on differing block sizes, called the long and short blocks, one embodiment of the present invention utilizes complex-valued premultiplication and postmultiplication steps which prepare and arrange the data samples so that both the long and short block transforms may be computed with a computationally efficient FFT.
    Type: Grant
    Filed: February 26, 1999
    Date of Patent: August 6, 2002
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventor: Shay-Jan Huang
  • Patent number: 6327691
    Abstract: The present invention comprises an efficient system and method for computing and encoding error detection sequences in digital audio encoding. In one embodiment, an AC-3 encoder appends a cyclic redundancy check (CRC) frame check sequence at the front of each data frame. Furthermore, this frame check sequence may be evaluated in the same kind of circuitry that is used to evaluate the CRC frame check sequence appended at the end of each data frame. In one embodiment of the present invention, a shift register contains feedback elements located in reference to a generating polynomial derived from the given generating polynomial for the CRC frame check sequence appended at the end of each data frame. The data bits are sent through the shift register in reverse time order, and, upon sending the last data bit in reverse time order, the shift register contains the required CRC frame check sequence.
    Type: Grant
    Filed: February 12, 1999
    Date of Patent: December 4, 2001
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventor: Shay-Jan Huang