Patents by Inventor Shay Mizrachi
Shay Mizrachi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10509876Abstract: A method for design simulation includes partitioning a verification task of a design (100) into a first plurality of atomic Processing Elements (PEs—108) having execution dependencies (112), each execution dependency specifying that a respective first PE is to be executed before a respective second PE. The method further includes computing an order for executing the PEs on a multiprocessor device (32), which includes a second plurality of processors (44) operating in parallel and schedules the PEs for execution by the processors according to a built-in scheduling policy. The order induces concurrent execution of the PEs by different ones of the processors without violating the execution dependencies, irrespective of the scheduling policy. The PEs are executed on the processors in accordance with the computed order and the scheduling policy, to produce a simulation result. A performance of the design is verified responsively to the simulation result.Type: GrantFiled: June 3, 2015Date of Patent: December 17, 2019Assignee: Rocketick Technologies LTDInventors: Uri Tal, Shay Mizrachi, Tomer Ben-David
-
Patent number: 9684744Abstract: A method for design verification includes receiving a definition of a design of an integrated circuit device and at least one assertion of a property that is to be verified over the design. The definition is compiled into a graph of processing elements, including first processing elements that simulate operation of the device and at least one second processing element representing the at least one assertion. The at least one second processing element includes a hierarchical arrangement of at least one operator node and one or more leaf nodes corresponding to inputs of the at least one assertion. A simulation of the design is executed by triggering the processing elements in the graph in multiple, consecutive clock cycles and evaluating the property during execution of the simulation.Type: GrantFiled: October 15, 2015Date of Patent: June 20, 2017Assignee: Rocketick Technologies LTD.Inventors: Ishay Geller, Guy Rom, Shay Mizrachi
-
Patent number: 9684494Abstract: A computing method includes accepting a definition of a computing task, which includes multiple Processing Elements (PEs) having execution dependencies. The computing task is compiled for concurrent execution on a multiprocessor device, by arranging the PEs in a series of two or more invocations of the multiprocessor device, including assigning the PEs to the invocations depending on the execution dependencies. The multiprocessor device is invoked to run software code that executes the series of the invocations, so as to produce a result of the computing task.Type: GrantFiled: March 16, 2015Date of Patent: June 20, 2017Assignee: ROCKETICK TECHNOLOGIES LTD.Inventors: Shay Mizrachi, Uri Tal, Tomer Ben-David, Ishay Geller, Ido Kasher, Ronen Gal
-
Patent number: 9672065Abstract: A method includes accepting a simulation task for simulation by a simulator that controls multiple co-simulators. Each of the multiple co-simulators is assigned to execute one or more respective sub-tasks of the simulation task. The simulation task is executed by invoking each co-simulator to execute the respective assigned sub-tasks.Type: GrantFiled: July 26, 2015Date of Patent: June 6, 2017Assignee: Rocketick Technologies LTDInventors: Shay Mizrachi, Uri Tal, Tomer Ben-David, Ishay Geller, Ido Kasher
-
Publication number: 20170109457Abstract: A method for design verification includes receiving a definition of a design of an integrated circuit device and at least one assertion of a property that is to be verified over the design. The definition is compiled into a graph of processing elements, including first processing elements that simulate operation of the device and at least one second processing element representing the at least one assertion. The at least one second processing element includes a hierarchical arrangement of at least one operator node and one or more leaf nodes corresponding to inputs of the at least one assertion. A simulation of the design is executed by triggering the processing elements in the graph in multiple, consecutive clock cycles and evaluating the property during execution of the simulation.Type: ApplicationFiled: October 15, 2015Publication date: April 20, 2017Inventors: Ishay Geller, Guy Rom, Shay Mizrachi
-
Publication number: 20160019326Abstract: A method for design simulation includes partitioning a verification task of a design (100) into a first plurality of atomic Processing Elements (PEs-108) having execution dependencies (112), each execution dependency specifying that a respective first PE is to be executed before a respective second PE. The method further includes computing an order for executing the PEs on a multiprocessor device (32), which includes a second plurality of processors (44) operating in parallel and schedules the PEs for execution by the processors according to a built-in scheduling policy. The order induces concurrent execution of the PEs by different ones of the processors without violating the execution dependencies, irrespective of the scheduling policy. The PEs are executed on the processors in accordance with the computed order and the scheduling policy, to produce a simulation result. A performance of the design is verified responsively to the simulation result.Type: ApplicationFiled: June 3, 2015Publication date: January 21, 2016Inventors: Uri Tal, Shay Mizrachi, Tomer Ben-David
-
Method and system for supplying power to multiple voltage islands using a single supply source (SSS)
Patent number: 9239600Abstract: Methods and systems for supplying power to multiple voltage islands using a single supply source are disclosed. Aspects of one method may include providing power to a first of a plurality of voltage islands, and individually controlling providing of power to each of a remaining portion of the plurality of voltage islands. For example, when an electronic system is first powered on, a low current voltage source may be used to supply power to a primary voltage island. As a higher current voltage source becomes available, power derived from the higher current voltage source may be provided to the primary voltage island and to secondary voltage islands. Power to each of the secondary voltage islands may be, for example, individually controlled via a power MOS transistor. The power MOS transistor may also be configured to allow a faster blocking time than unblocking time.Type: GrantFiled: March 29, 2012Date of Patent: January 19, 2016Assignee: Broadcom CorporationInventors: Ariel Pickholz, Long Nguyen, Shay Mizrachi -
Publication number: 20150331713Abstract: A method includes accepting a simulation task for simulation by a simulator that controls multiple co-simulators. Each of the multiple co-simulators is assigned to execute one or more respective sub-tasks of the simulation task. The simulation task is executed by invoking each co-simulator to execute the respective assigned sub-tasks.Type: ApplicationFiled: July 26, 2015Publication date: November 19, 2015Inventors: Shay Mizrachi, Uri Tal, Tomer Ben-David, Ishay Geller, Ido Kasher
-
Patent number: 9128748Abstract: A method includes accepting a simulation task for simulation by a simulator that controls multiple co-simulators. Each of the multiple co-simulators is assigned to execute one or more respective sub-tasks of the simulation task. The simulation task is executed by invoking each co-simulator to execute the respective assigned sub-tasks.Type: GrantFiled: April 12, 2011Date of Patent: September 8, 2015Assignee: ROCKETICK TECHNOLOGIES LTD.Inventors: Shay Mizrachi, Uri Tal, Tomer Ben-David, Ishay Geller, Ido Kasher
-
Patent number: 9087166Abstract: A method for design simulation includes partitioning a verification task of a design (100) into a first plurality of atomic Processing Elements (PEs-108) having execution dependencies (112), each execution dependency specifying that a respective first PE is to be executed before a respective second PE. The method further includes computing an order for executing the PEs on a multiprocessor device (32), which includes a second plurality of processors (44) operating in parallel and schedules the PEs for execution by the processors according to a built-in scheduling policy. The order induces concurrent execution of the PEs by different ones of the processors without violating the execution dependencies, irrespective of the scheduling policy. The PEs are executed on the processors in accordance with the computed order and the scheduling policy, to produce a simulation result. A performance of the design is verified responsively to the simulation result.Type: GrantFiled: April 28, 2014Date of Patent: July 21, 2015Assignee: ROCKETICK TECHNOLOGIES LTD.Inventors: Uri Tal, Shay Mizrachi, Tomer Ben-David
-
Publication number: 20150186120Abstract: A computing method includes accepting a definition of a computing task, which includes multiple Processing Elements (PEs) having execution dependencies. The computing task is compiled for concurrent execution on a multiprocessor device, by arranging the PEs in a series of two or more invocations of the multiprocessor device, including assigning the PEs to the invocations depending on the execution dependencies. The multiprocessor device is invoked to run software code that executes the series of the invocations, so as to produce a result of the computing task.Type: ApplicationFiled: March 16, 2015Publication date: July 2, 2015Inventors: Shay Mizrachi, Uri Tal, Tomer Ben-David, Ishay Geller, Ido Kasher, Ronen Gal
-
Patent number: 9032377Abstract: A computing method includes accepting a definition of a computing task, which includes multiple Processing Elements (PEs) having execution dependencies. The computing task is compiled for concurrent execution on a multiprocessor device, by arranging the PEs in a series of two or more invocations of the multiprocessor device, including assigning the PEs to the invocations depending on the execution dependencies. The multiprocessor device is invoked to run software code that executes the series of the invocations, so as to produce a result of the computing task.Type: GrantFiled: June 2, 2013Date of Patent: May 12, 2015Assignee: Rocketick Technologies Ltd.Inventors: Shay Mizrachi, Uri Tal, Tomer Ben-David, Ishay Geller, Ido Kasher, Ronen Gal
-
Publication number: 20140379320Abstract: A method for design simulation includes partitioning a verification task of a design (100) into a first plurality of atomic Processing Elements (PEs-108) having execution dependencies (112), each execution dependency specifying that a respective first PE is to be executed before a respective second PE. The method further includes computing an order for executing the PEs on a multiprocessor device (32), which includes a second plurality of processors (44) operating in parallel and schedules the PEs for execution by the processors according to a built-in scheduling policy. The order induces concurrent execution of the PEs by different ones of the processors without violating the execution dependencies, irrespective of the scheduling policy. The PEs are executed on the processors in accordance with the computed order and the scheduling policy, to produce a simulation result. A performance of the design is verified responsively to the simulation result.Type: ApplicationFiled: April 28, 2014Publication date: December 25, 2014Applicant: ROCKETICK TECHNOLOGIES LTD.Inventors: Uri Tal, Shay Mizrachi, Tomer Ben-David
-
Patent number: 8751211Abstract: A method for design simulation includes partitioning a verification task of a design into a first plurality of atomic Processing Elements (PEs) having execution dependencies, each execution dependency specifying that a respective first PE is to be executed before a respective second PE. The method further includes computing an order for executing the PEs on a multiprocessor device, which includes a second plurality of processors operating in parallel and schedules the PEs for execution by the processors according to a built-in scheduling policy. The order induces concurrent execution of the PEs by different ones of the processors without violating the execution dependencies irrespective of the scheduling policy. The PEs are executed on the processors in accordance with the computed order and the scheduling policy, to produce a simulation result. A performance of the design is verified responsively to the simulation result.Type: GrantFiled: March 25, 2009Date of Patent: June 10, 2014Assignee: Rocketick Technologies Ltd.Inventors: Uri Tal, Shay Mizrachi, Tomer Ben-David
-
Patent number: 8725893Abstract: Certain aspects of a method and system for configuring a plurality of network interfaces that share a physical interface (PHY) may include a system comprising one or more physical network interface controllers (NICs) and two or more virtual NICs. One or more drivers associated with each of the virtual NICs that share one or more Ethernet ports associated with the physical NICs may be synchronized based on controlling one or more parameters associated with one or more Ethernet ports. One or more wake on LAN (WoL) patterns associated with each of the drivers may be detected at one or more Ethernet ports. A wake up signal may be communicated to one or more drivers associated with the detected WoL patterns. One of the drivers may be appointed to be a port master driver. If a failure of the appointed port master driver is detected, another driver may be appointed to be the port master driver.Type: GrantFiled: April 11, 2011Date of Patent: May 13, 2014Assignee: Broadcom CorporationInventors: Eliezer Tamir, Uri Tal, Shay Mizrachi
-
Publication number: 20130263100Abstract: A computing method includes accepting a definition of a computing task, which includes multiple Processing Elements (PEs) having execution dependencies. The computing task is compiled for concurrent execution on a multiprocessor device, by arranging the PEs in a series of two or more invocations of the multiprocessor device, including assigning the PEs to the invocations depending on the execution dependencies. The multiprocessor device is invoked to run software code that executes the series of the invocations, so as to produce a result of the computing task.Type: ApplicationFiled: June 2, 2013Publication date: October 3, 2013Inventors: Shay Mizrachi, Uri Tal, Tomer Ben-David, Ishay Geller, Ido Kasher, Ronen Gal
-
Patent number: 8516454Abstract: A computing method includes accepting a definition of a computing task (68), which includes multiple atomic Processing Elements (PEs—76) having execution dependencies (80). Each execution dependency specifies that a respective first PE is to be executed before a respective second PE. The computing task is compiled for concurrent execution on a multiprocessor device (32), which includes multiple processors (44) that are capable of executing a first number of the PEs simultaneously, by arranging the PEs, without violating the execution dependencies, in an invocation data structure (90) including a second number of execution sequences (98) that is greater than one but does not exceed the first number. The multiprocessor device is invoked to run software code that executes the execution sequences in parallel responsively to the invocation data structure, so as to produce a result of the computing task.Type: GrantFiled: June 30, 2009Date of Patent: August 20, 2013Assignee: Rocketick Technologies Ltd.Inventors: Shay Mizrachi, Uri Tal, Tomer Ben-David
-
Patent number: 8478907Abstract: A network interface device for use with a host computer that includes a host processor and a memory, and which is configured to concurrently run a master operating system and at least one virtual operating system. The device includes a bus interface that communicates over a bus with the host processor and the memory, and a network interface, which is coupled to send and receive data packets carrying data over a packet network. A protocol processor is coupled between the bus interface and the network interface so as to convey the data between the network interface and the memory while performing protocol processing on the data packets under instructions from the at least one virtual operating system, while bypassing the master operating system.Type: GrantFiled: May 3, 2006Date of Patent: July 2, 2013Assignee: Broadcom CorporationInventors: Eliezer Aloni, Kobby Carmona, Shay Mizrachi, Rafi Shalom, Merav Sicron, Dov Hirshfeld, Amit Oren, Caitlin Bestler, Uri Tal, Uri Elzur, Kan (Frankie) Fan, Scott McDaniel
-
Patent number: 8416768Abstract: Certain aspects of a method and system for transparent transmission control protocol (TCP) offload with best effort direct placement of incoming traffic are disclosed. Aspects of a method may include collecting TCP segments in a network interface card (NIC) processor without transferring state information to a host processor every time a TCP segment is received. When an event occurs that terminates the collection of TCP segments, the NIC processor may generate a new aggregated TCP segment based on the collected TCP segments. If a placement sequence number corresponding to the generated new TCP segment for the particular network flow is received before the TCP segment is received, the generated new TCP segment may be transferred directly from the memory to the user buffer instead of transferring the data to a kernel buffer, which would require further copy by the host stack from kernel buffer to user buffer.Type: GrantFiled: April 5, 2010Date of Patent: April 9, 2013Assignee: Broadcom Israel Research Ltd.Inventors: Eliezer Aloni, Rafi Shalom, Shay Mizrachi, Dov Hirshfeld, Aviv Greenberg, Assaf Grunfeld, Eliezer Tamir, Guy Corem, Ori Hanegbi
-
Patent number: 8274976Abstract: Certain aspects of a method and system for transparent transmission control protocol (TCP) offload are disclosed. Aspects of a method may include collecting TCP segments in a network interface card (NIC) processor without transferring state information to a host system. The collected TCP segments may be buffered in a coalescer. The coalescer may verify that the network flow associated with the collected TCP segments has an entry in a flow lookup table (FLT). When the FLT is full, the coalescer may close a current entry and assign the network flow to the available entry. The coalescer may also update information in the FLT. When an event occurs that terminates the collection of TCP segments, the coalescer may generate a single aggregated TCP segment based on the collected TCP segments. The aggregated TCP segment and state information may be communicated to the host system for processing.Type: GrantFiled: March 22, 2010Date of Patent: September 25, 2012Assignee: Broadcom CorporationInventors: Eliezer Aloni, Rafi Shalom, Shay Mizrachi, Dov Hirshfeld, Aviv Greenberg, Assaf Grunfeld, Eliezer Tamir, Guy Corem, Ori Hanegbi