Abstract: A level translator block receives a control signal and a data signal and provides an interface between circuitry operating in a first voltage domain and circuitry operating in a second voltage domain. Thick-oxide transistors are appropriately used in the level translator block to reduce gate leakage currents when translating signals.

Abstract: An integrated circuit having a state retentive memory structure to store state values. A high performance section uses thin gate-oxide transistors and the state retentive memory structure uses thick gate-oxide transistors to capture and retain the state values when operating in a low power mode.

Abstract: Techniques and apparatuses for reducing power consumption in processor based systems during active and standby modes. A low power TLB is disclosed that does not precharge invalid entries or write to output circuits physical addresses that are the same as immediately preceding lookups. A circuit to acknowledge that the integrated circuits of the processor have entered low power standby mode that is low leakage and consumes little power is disclosed. Minimum delay buffers that have very low leakage because of series placement of a long delay enable transistor with the transistors of the inverters that make up the buffers is also disclosed.

Abstract: An integrated circuit having a state retentive memory structure to store state values. A high performance section uses thin gate-oxide transistors and the state retentive memory structure uses thick gate-oxide transistors to capture and retain the state values when operating in a low power mode.

Abstract: A level translator block receives a control signal and a data signal and provides an interface between circuitry operating in a first voltage domain and circuitry operating in a second voltage domain. Thick-oxide transistors are appropriately used in the level translator block to reduce gate leakage currents when translating signals.