Patents by Inventor Shay P. Seng

Shay P. Seng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8769449
    Abstract: Methods for generating a circuit design are disclosed. A plurality of cells is instantiated in the circuit design in response to user input. The set of interface parameters of each cell is arranged into a hierarchy of interface levels as indicated by an interface model corresponding to the cell. For each of the interface levels, values of the sets of interface parameters of cells included in the interface level are respectively propagated to other cells directly connected to the cell. In response to propagating a value of an interface parameter from another cell of the plurality of cells to the cell and the cell having a value of the corresponding interface parameter that is different from the propagated value, a value for the corresponding interface parameter of the cell is determined using a respective propagation function associated with the corresponding interface level.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: July 1, 2014
    Assignee: Xilinx, Inc.
    Inventors: Adam P. Donlin, Biping Wu, Kyle Corbett, Nabeel Shirazi, Shay P. Seng, Amit Kasat, Srinivas Beeravolu, Khang K. Dao, Jeffrey H. Seltzer, Christopher J. Case
  • Patent number: 8635567
    Abstract: A method of circuit design includes receiving a user input selecting a first interface of a circuit block of a circuit design as a source interface in creating a connection within the circuit design and selecting a second interface of the circuit design as a candidate destination interface for the connection using a processor. The method further includes determining compatibility between the second interface and the first interface and indicating compatibility of the second interface with the first interface for the connection.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: January 21, 2014
    Assignee: Xilinx, Inc.
    Inventors: Shay P. Seng, Krishnan Subramanian, Robert E. Shortt
  • Patent number: 8595684
    Abstract: A method is provided for generation of a circuit design. A set of design assistance rules is retrieved from a database. Each design assistance rule in the set includes a list of design objects to which the design assistance rule applies, a set of criteria to be satisfied by the circuit design before the design assistance rule may be applied, a set of configuration options, and an executable script configured to perform an automated configuration of the circuit design. In response to a change in the circuit design, applicable design assistance rules are determined based on the corresponding sets of criteria. In response to determining that one or more design assistance rules are applicable, data indicating that the one or more design assistance rules are available is output. In response to input that selects a design assistance rule the executable script corresponding to the selected design assistance rule is executed.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: November 26, 2013
    Assignee: Xilinx, Inc.
    Inventors: Shay P. Seng, Amit Kasat
  • Patent number: 8145466
    Abstract: Approaches for preparing simulation models of an electronic circuit are disclosed. The design is partitioned into first and second clusters. The design includes a source module in the first cluster connected to a destination module in the second cluster. The first cluster is compiled into a first model for a software-based co-simulation platform for simulating behavior of the source module using the first model. The first cluster and the second cluster of the design are compiled into a second model for a hardware-based co-simulation platform that includes a programmable logic circuit configurable for emulating behavior of the design using the second model. An interconnection block is generated and stored in the second model. The interconnection block is switchable between coupling of the destination module in the second model to the source module of the first model or to a source module of the second model.
    Type: Grant
    Filed: May 21, 2009
    Date of Patent: March 27, 2012
    Assignee: Xilinx, Inc.
    Inventors: Chi Bun Chan, Jingzhao Ou, Haibing Ma, Shay P. Seng