Patents by Inventor Shay Segev

Shay Segev has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240192889
    Abstract: The present disclosure generally relates to improved fragment processing while command fetching is on-going. Rather than stopping command fetching, the controller uses a short fragment list, while command fetching can continue, to add a fragment. The controller first adds new fragments to the short list with the fragment information. The information is then checked for size. If the fragment information is smaller than the short fragment list, then the fragment list is updated during command fetching. As a command arrives, the controller does a binary search of a sorted fragment list. The results are stored and later scanned by the controller for matches with the short fragment list. If there are no matches in the short list, then the controller uses the stored results to update the search result. If there is a match in the short list then the controller uses the new results to update the search list.
    Type: Application
    Filed: July 19, 2023
    Publication date: June 13, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Amir SEGEV, Shay BENISTY
  • Publication number: 20240168801
    Abstract: The present disclosure generally relate to improved tenant processing by arbitration of commands. Rather than processing a tenant with multiple portions to completion causing increased wait time for preceding tenants, allowing the controller to process commands based on the respective bandwidth allocated to each tenant is beneficial. Through a Weighted Round Robin (WRR) arbiter, the controller is able to allocate a percentage of the bandwidth to each tenant based on the tenant's needs. Once the bandwidth is allocated to the tenants, the controller may then process portions of the commands from the tenants up to the allocated bandwidth per tenant, which avoids the need for commands that are fetched after earlier commands wait for previous commands to complete their processing, but instead process all command portions based on the allocated bandwidth from the WRR arbiter.
    Type: Application
    Filed: July 26, 2023
    Publication date: May 23, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Amir SEGEV, Shay BENISTY
  • Patent number: 11983428
    Abstract: Systems and methods for data migration via a peer communication channel between data storage devices are disclosed. The data storage devices include a host interface configured to connect to at least one host system and a peer interface to connect to the peer communication channel, where the host interface and the peer interface and separate physical interfaces. A source data storage device establishes peer communication with a destination data storage device over the peer communication channel, determines a set of host data, and sends the set of host data to the destination data storage device, while continuing to receive and process host storage operations through the host interface.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: May 14, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Shay Benisty, Amir Rozen, Amir Segev
  • Publication number: 20240152293
    Abstract: The present disclosure generally relates to memory management during SGL fetching. When a data storage device is required to fetch an SGL from a host device, the data storage device cannot determine how much memory will be required to be allocated. The disclosure herein reduces the impact of the problem of under or over allocating memory and over-fetching, thereby reducing performance of the device during transfers. The disclosure provides guidance on how to implement an adaptive learning process based upon statistic collection of SGL fetches. By maintaining a table of statistics, the data storage device controller may learn and more closely predict an amount of memory to allocate for SGL fetching.
    Type: Application
    Filed: July 12, 2023
    Publication date: May 9, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Amir SEGEV, Shay BENISTY
  • Publication number: 20240143228
    Abstract: The present disclosure generally relates to read and write operations utilizing barrier commands. Using barrier commands and a snapshot of doorbell states of submission queues (SQs), the necessary write commands to perform a read may be identified and executed to reduce any wait time of the host. As such, host delays during reads and writes are reduced. In absence of a barrier command, the host needs to wait for writes to complete before performing a read. When a barrier command is used, the host needs to wait for the barrier command to complete before performing a read. The controller will execute the post barrier reads only after completing the pre-barrier writes. As will be discussed herein, the controller completes the barrier command as soon as a doorbell snapshot is taken even though the pre-barrier writes may not yet be completed.
    Type: Application
    Filed: July 12, 2023
    Publication date: May 2, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Amir SEGEV, Shay BENISTY, Rotem SELA
  • Publication number: 20240143508
    Abstract: The present disclosure generally relates to improved address translation. Rather than fetching translated addresses using ATS/ATC, a HIM address translation search engine (HATS) is used through implementing the ATC in a layer above per an NVMe command. The HATS is an engine that will monitor pointers with untranslated addresses and will fetch the translated addresses for the pointers. Once the translated addresses are fetched for the pointer, the HATS will overwrite the untranslated address with the translated address. The HATS will then update the status of the pointers. When a translation request fails, the device will use PRI to request the translated address. During a translation request fail the device will drain any incoming requests while skipping the data transfer phase. The device will not block any other requests in a queue. Once that translated address is received through the PRI flow, the status of the pointer will be updated.
    Type: Application
    Filed: July 26, 2023
    Publication date: May 2, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Shay BENISTY, Amir SEGEV
  • Publication number: 20240094950
    Abstract: The present disclosure generally relates to improved access to the DRAM using namespace mapping. The PMR address range is mapped to LBA address space. Mapping the PMR address range in LBA address space allows the host to access the PMR indirectly using NVMe commands. The host device may hold in the namespace the most frequently accessed data and obtain highest performance and low latency. Implementation of the Power Loss Protection (PLP) feature over the PMR makes the system prefer storing the data in PMR rather in host memory. All internal SRAMs (e.g. Transfer RAMs, XOR RAMs, etc.) may be mapped in the LBA address space so the host device can access mainly for debug purposes. Some internal flops that hold important data are mapped in the LBA address space as well.
    Type: Application
    Filed: September 16, 2022
    Publication date: March 21, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Shay BENISTY, Amir SEGEV, Judah Gamliel HAHN
  • Patent number: 11934684
    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to determine a maximum bandwidth of an interface, allocate a portion of the maximum bandwidth to one or more tenants, either: determine a maximum data transfer size (MDTS) setting based on quality of service (QoS) requirements, determine an aggregated queue depth (QD) setting based on QoS requirements, or determine a combined MDTS and aggregated QD setting based on QoS requirements, and provide the determined settings to the one or more tenants.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: March 19, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Amir Segev, Shay Benisty
  • Patent number: 11934693
    Abstract: The present disclosure generally relates to data storage devices, such as solid state drives (SSDs), specifically utilizing the data storage device memory in the execution of host commands. A controller is configured to receive a command pointer or a data chunk from a host device, mark a destination used for the command pointer or the data chunk, determine whether a last chunk of the command pointer or the data chunk has been received, and determine whether the command pointer or the data chunk uses an illegal combination of locations after determining that the last chunk of the command pointer has been received. The controller is further configured to return an error message to the host device upon determining that the command pointer or the data chunk uses an illegal combination of locations.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: March 19, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Amir Segev, Shay Benisty
  • Patent number: 11914900
    Abstract: A storage system receives an instruction to cancel an in-progress read/write command. The storage system allows data associated with the command to continue to be processed by a data path in the storage system even though the command was cancelled. However, before the data is actually transferred out of the data path, a controller determines that the command was cancelled and prevents the data from being transferred out, while internally indicating that the transfer was complete. This provides a faster cancellation process than methods that attempt to stop the data from being processed by the data path.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: February 27, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Amir Segev, Shay Benisty
  • Patent number: D874671
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: February 4, 2020
    Inventor: Shay Segev
  • Patent number: D874672
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: February 4, 2020
    Inventor: Shay Segev
  • Patent number: D875676
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: February 18, 2020
    Inventor: Shay Segev
  • Patent number: D884203
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: May 12, 2020
    Inventor: Shay Segev