Patents by Inventor She-Hsin Hsiao

She-Hsin Hsiao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11575030
    Abstract: A heterojunction bipolar transistor includes an emitter layer on a base layer on a collector layer on an upper sub-collector layer over a bottom sub-collector layer, a first dielectric film over the bottom sub-collector layer, the base layer and the emitter layer, a base electrode on the first dielectric film, electrically connected to the base layer through at least one first via hole in the first dielectric film, a second dielectric film on the first dielectric film and the base electrode, and a conductive layer on the second dielectric film, with conductive layer electrically connected to base electrode through a second via hole disposed in the second dielectric film, first dielectric film between the base electrode and first sidewall of a stack including the base layer and the collector layer, and second via hole laterally separated from the base layer.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: February 7, 2023
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: She-Hsin Hsiao, Rong-Hao Syu, Shu-Hsiao Tsai
  • Patent number: 11411080
    Abstract: A heterojunction bipolar transistor includes a bottom sub-collector layer formed over a substrate. The heterojunction bipolar transistor also includes an upper sub-collector layer formed over the bottom sub-collector layer. The heterojunction bipolar transistor also includes a collector layer formed over the upper sub-collector layer. The heterojunction bipolar transistor also includes a base layer formed over the collector layer. The heterojunction bipolar transistor also includes an emitter layer formed over the base layer. The heterojunction bipolar transistor also includes a passivation layer covering the bottom sub-collector layer, the upper sub-collector layer, the collector layer, the base layer, and the emitter layer. The heterojunction bipolar transistor also includes a collector electrode that covers the portion of the passivation layer that is over the sidewall of the upper sub-collector layer.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: August 9, 2022
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Chien-Rong Yu, Shu-Hsiao Tsai, Jui-Pin Chiu, She-Hsin Hsiao
  • Publication number: 20220216303
    Abstract: A heterojunction bipolar transistor includes a bottom sub-collector layer formed over a substrate. The heterojunction bipolar transistor also includes an upper sub-collector layer formed over the bottom sub-collector layer. The heterojunction bipolar transistor also includes a collector layer formed over the upper sub-collector layer. The heterojunction bipolar transistor also includes a base layer formed over the collector layer. The heterojunction bipolar transistor also includes an emitter layer formed over the base layer. The heterojunction bipolar transistor also includes a passivation layer covering the bottom sub-collector layer, the upper sub-collector layer, the collector layer, the base layer, and the emitter layer. The heterojunction bipolar transistor also includes a collector electrode that covers the portion of the passivation layer that is over the sidewall of the upper sub-collector layer.
    Type: Application
    Filed: January 5, 2021
    Publication date: July 7, 2022
    Inventors: Chien-Rong YU, Shu-Hsiao TSAI, Jui-Pin CHIU, She-Hsin HSIAO
  • Publication number: 20220052188
    Abstract: A heterojunction bipolar transistor includes an emitter layer on a base layer on a collector layer on an upper sub-collector layer over a bottom sub-collector layer, a first dielectric film over the bottom sub-collector layer, the base layer and the emitter layer, a base electrode on the first dielectric film, electrically connected to the base layer through at least one first via hole in the first dielectric film, a second dielectric film on the first dielectric film and the base electrode, and a conductive layer on the second dielectric film, with conductive layer electrically connected to base electrode through a second via hole disposed in the second dielectric film, first dielectric film between the base electrode and first sidewall of a stack including the base layer and the collector layer, and second via hole laterally separated from the base layer.
    Type: Application
    Filed: October 14, 2021
    Publication date: February 17, 2022
    Inventors: She-Hsin Hsiao, Rong-Hao Syu, Shu-Hsiao Tsai
  • Patent number: 11177374
    Abstract: A heterojunction bipolar transistor includes an emitter layer on a base layer on a collector layer on an upper sub-collector layer over a bottom sub-collector layer, a first dielectric film over the bottom sub-collector layer, the base layer and the emitter layer, a base electrode on the first dielectric film, electrically connected to the base layer through at least one first via hole in the first dielectric film, a second dielectric film on the first dielectric film and the base electrode, and a conductive layer on the second dielectric film, with conductive layer electrically connected to base electrode through a second via hole disposed in the second dielectric film, first dielectric film between the base electrode and first sidewall of a stack including the base layer and the collector layer, and second via hole laterally separated from the base layer.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: November 16, 2021
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: She-Hsin Hsiao, Rong-Hao Syu, Shu-Hsiao Tsai