Patents by Inventor Sheau Hooi Lim

Sheau Hooi Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Stress-relief layers and stress-compensation collars with low-temperature solders for board-level joints, and processes of making same
    Patent number: 7291548
    Abstract: A stress-relief layer is formed by dispensing a polymer upon a substrate lower surface under conditions to partially embed a low melting-point solder bump that is disposed upon the lower surface. The stress-relief layer flows against the low melting-point solder bump. A stress-compensation collar is formed on a board to which the substrate is mated, and the stress-compensation collar partially embeds the low melting-point solder bump. An article that exhibits a stress-relief layer and a stress-compensation collar is also included. A computing system that includes the low melting-point solder, the stress-relief layer, and the stress-compensation collar is also included.
    Type: Grant
    Filed: April 17, 2007
    Date of Patent: November 6, 2007
    Assignee: Intel Corporation
    Inventors: Daewoong Suh, Saikumar Jayaraman, Stephen E. Lehman, Mitesh Patel, Tiffany A. Byrne, Edward L. Martin, Mohd Erwan B. Basiron, Wei Keat Loh, Sheau Hooi Lim, Yoong Tatt P. Chin
  • Stress-relief layers and stress-compensation collars with low-temperature solders for board-level joints, and processes of making same
    Patent number: 7253088
    Abstract: A stress-relief layer is formed by dispensing a polymer upon a substrate lower surface under conditions to partially embed a low melting-point solder bump that is disposed upon the lower surface. The stress-relief layer flows against the low melting-point solder bump. A stress-compensation collar is formed on a board to which the substrate is mated, and the stress-compensation collar partially embeds the low melting-point solder bump. An article that exhibits a stress-relief layer and a stress-compensation collar is also included. A computing system that includes the low melting-point solder, the stress-relief layer, and the stress-compensation collar is also included.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: August 7, 2007
    Assignee: Intel Corporation
    Inventors: Daewoong Suh, Saikumar Jayaraman, Stephen E. Lehman, Mitesh Patel, Tiffany A. Byrne, Edward L. Martin, Mohd Erwan B. Basiron, Wei Keat Loh, Sheau Hooi Lim, Yoong Tatt P. Chin
  • Stress-relief layer and stress-compensation collar in contact arrays, and processes of making same
    Patent number: 7244634
    Abstract: A stress-relief layer is formed by dispensing a polymer upon a substrate lower surface under conditions to partially embed a solder bump that is disposed upon the lower surface. The stress-relief layer flows against the solder bump. A stress-compensation collar is formed on a board to which the substrate is mated and the SCC partially embeds the solder bump. An article that exhibits a stress-relief layer and a stress-compensation collar is also included. A computing system that includes a stress-relief layer and a stress-compensation collar is also included.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: July 17, 2007
    Assignee: Intel Corporation
    Inventors: Daewoong Suh, Saikumar Jayaraman, Mohd Erwan P. Bin Basiron, Sheau Hooi Lim, Yoong Tatt P. Chin
  • Chip packaging compositions, packages and systems made therewith, and methods of making same
    Patent number: 7088010
    Abstract: A system for chip packaging includes an adamantoid packaging composition. The adamantoid composition ameliorates the CTE mismatch that typically exists between a packaged die and a resin-impregnated fiberglass mounting substrate. In an embodiment, the system includes a packaging composition that alone exhibits a CTE that is characteristic of an inorganic-filled underfill composite previously known. An embodiment is also directed to the assembly of a chip package that uses an adamantoid packaging composition.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: August 8, 2006
    Assignee: Intel Corporation
    Inventors: Sheau Hooi Lim, Choong Kooi Chee
  • Stress-relief layers and stress-compensation collars with low-temperature solders for board-level joints, and processes of making same
    Publication number: 20060068579
    Abstract: A stress-relief layer is formed by dispensing a polymer upon a substrate lower surface under conditions to partially embed a low melting-point solder bump that is disposed upon the lower surface. The stress-relief layer flows against the low melting-point solder bump. A stress-compensation collar is formed on a board to which the substrate is mated, and the stress-compensation collar partially embeds the low melting-point solder bump. An article that exhibits a stress-relief layer and a stress-compensation collar is also included. A computing system that includes the low melting-point solder, the stress-relief layer, and the stress-compensation collar is also included.
    Type: Application
    Filed: September 29, 2004
    Publication date: March 30, 2006
    Inventors: Daewoong Suh, Saikumar Jayaraman, Stephen Lehman, Mitesh Patel, Tiffany Byrne, Edward Martin, Mohd Erwan Basiron, Wei Keat Loh, Sheau Hooi Lim, Yoong Tatt Chin