Abstract: A memory operate in a normal mode of operation or a testing mode of operation. In the testing mode of operation, the memory can measure various benchmarks of performance, such as read speed. The memory can perform an asynchronous read operation to read a word of electronic data that corresponds to an address or a page read operation in which multiple asynchronous read operations are performed to read multiple words of electronic data, also referred to as a page of electronic data, that correspond to multiple addresses. The memory can measure a time required, referred to as read speed, to read the word of electronic data or the multiple words of electronic data from the memory.

Abstract: A memory is disclosed that can operate in a normal mode of operation or a testing mode of operation. In the testing mode of operation, the memory can measure various benchmarks of performance, such as read speed. The memory can perform an asynchronous read operation to read a word of electronic data that corresponds to an address or a page read operation in which multiple asynchronous read operations are performed to read multiple words of electronic data, also referred to as a page of electronic data, that correspond to multiple addresses. The memory can measure a time required, referred to as read speed, to read the word of electronic data or the multiple words of electronic data from the memory.

Abstract: A method, system and apparatus for determining whether any un-programmed cell is affected by charge disturb by comparing the voltage threshold of the un-programmed cells against a reference voltage. If the voltage threshold for the un-programmed cell exceeds the reference voltage, the failed or defective un-programmed cell will be then be programmed. This will change the defective un-programmed cell to a new programmed value. To account for the location of the failing memory cell, address syndrome bits are used to identify the location of the defective memory cell.

Abstract: A method, system and apparatus for determining whether any un-programmed cell is affected by charge disturb by comparing the voltage threshold of the un-programmed cells against a reference voltage. If the voltage threshold for the un-programmed cell exceeds the reference voltage, the failed or defective un-programmed cell will be then be programmed. This will change the defective un-programmed cell to a new programmed value. To account for the location of the failing memory cell, address syndrome bits are used to identify the location of the defective memory cell.

Abstract: Systems and methods for producing a boosted voltage which can be used as a boosted word line voltage for read mode operations of memory cells are disclosed. The system contains a VCC comparator, a look up table, and a boosting circuit including a set of boosting capacitors. The look up table has a list of trim codes that indicates desired boosting ratios. The boosting ratio can vary depending on a level of a supply voltage to provide a sufficient word line voltage, thereby preventing and/or mitigating delay in reading operations. The number of the capacitors in the boosting circuit can be predetermined to be turned on or off according to the trim code. Accordingly, the voltage boost circuit provides a sufficient boosted word line voltage to a core cell gate with flexibility despite fluctuation of the supply voltage level.

Abstract: Systems and/or methods that facilitate accessing data in a memory are presented. The memory can be flash memory that includes a plurality of sectors in an array that can be associated with a decoder component that includes a regulator component, which facilitates performing read operations within a desired period of time. Each sector can be associated with a decoder subcomponent and associated regulator subcomponent. Parasitic resistance and capacitance elements can increase the further in distance a sector and associated decoder component are from a booster component, which is utilized to increase the voltage at a boost-strap node within each decoder subcomponent to facilitate performing read operations. To counter the parasitic elements, each regulator subcomponent can include one or more capacitors, where the number of capacitors and total capacitance value can be determined based on the distance the associated decoder subcomponent is from the booster component.

Abstract: Systems and methods for producing a boosted voltage which can be used as a boosted word line voltage for read mode operations of memory cells are disclosed. The system contains a VCC comparator, a look up table, and a boosting circuit including a set of boosting capacitors. The look up table has a list of trim codes that indicates desired boosting ratios. The boosting ratio can vary depending on a level of a supply voltage to provide a sufficient word line voltage, thereby preventing and/or mitigating delay in reading operations. The number of the capacitors in the boosting circuit can be predetermined to be turned on or off according to the trim code. Accordingly, the voltage boost circuit provides a sufficient boosted word line voltage to a core cell gate with flexibility despite fluctuation of the supply voltage level.

Abstract: Systems and/or methods that facilitate accessing data in a memory are presented. The memory can be flash memory that includes a plurality of sectors in an array that can be associated with a decoder component that includes a regulator component, which facilitates performing read operations within a desired period of time. Each sector can be associated with a decoder subcomponent and associated regulator subcomponent. Parasitic resistance and capacitance elements can increase the further in distance a sector and associated decoder component are from a booster component, which is utilized to increase the voltage at a boost-strap node within each decoder subcomponent to facilitate performing read operations. To counter the parasitic elements, each regulator subcomponent can include one or more capacitors, where the number of capacitors and total capacitance value can be determined based on the distance the associated decoder subcomponent is from the booster component.

Abstract: An apparatus having a code strip carrier that is illuminated by an illumination system and a plurality of read heads is disclosed. Each code track includes a plurality of dark and light stripes. Each read head is positioned to detect light from a corresponding one of the code tracks as that code track moves relative to the read head, the read head generating a signal indicative of the intensity of light reaching that read head. One of the code tracks includes a first absolute position track that provides an indication of the absolute position value when the code strip carrier is at each of a plurality of predetermined absolute positions relative to the origin position. A different one of the code tracks includes an incremental position track for generating a digital value indicative of a displacement of the code strip carrier relative to the last predetermined absolute position.