Abstract: A read only memory device includes multiple word lines, a first and second main bit line GL (n) and BL (n), sub-bit lines SB1 (n) to SB4 (n), selection switches MB1 (n) to MB4 (n), and memory cells M1 (n) to M4 (n). The memory cells M1 (n) to M4 (n) are electrically coupled to the sub-bit lines SB1 (n) to SB4 (n) and the sub-bit line SB1 (n+1), respectively. When the memory cell M3 (n) which is connected to SB3 (n) is read, the sub-bit lines SB1 (n) to SB3 (n) are connected to the corresponding main bit lines through the turned selection switches. At this time, the sub-bit lines SB1 (n) to SB3 (n) are not floating but are all at the same high voltage level. Therefore, the capacitance effect will not exist between them to change the voltage level of the sub-bit lines quickly.

Abstract: A read only memory device is made up of multiple word lines that are positioned in parallel to each other. The read only memory device includes an nth section, which includes a first main bit line GL (n) and a second main bit line BL (n); a first, a second, a third, and a fourth sub-bit lines SB1 (n) to SB4 (n); and a first, a second, a third, and a fourth selection switches MB1 (n) to MB4 (n), all of which are electrically coupled to the second bit line. The other terminal of the first selection switch MB1 (n) is electrically coupled to the first sub-bit line SB1 (n). The other terminals of each of the second and third selection switches MB2 (n) to MB3 (n) are electrically coupled to the third sub-bit line SB3 (n). The other terminal of the fourth selection switch MB4 (n) is electrically coupled to the first sub-bit line SB1 (n+1) of the (n+1)th section. The second and fourth sub-bit lines SB (2) and SB (4) are electrically coupled to the first main bit line GL (n).

Abstract: A sense amplifier circuit for sensing data fed to its data input terminal and operating on the data according to a pre-charge signal, a latch signal and a sense amplifier enable signal. The sense amplifier circuit includes a pre-charge sense circuit that receives data from a data input terminal and outputs a first output value as well as a latching circuit that receives the first output value and outputs a second output value within a preset period. The pre-charge sense circuit further includes a first circuit and a second circuit. The first circuit is capable of pre-charging the data input terminal to a preset potential level. The second circuit produces a first output value according to the input data. In addition, the first circuit and the second circuit are connected in parallel between a voltage source and a data input terminal.

Abstract: A multi-memory architecture and a memory access controller therefor are proposed. The multi-memory architecture is composed of at least two different types of memory devices and is used to provide a specific externally-accessible data storage capacity. The multi-memory architecture comprises a first memory device and a second memory device; wherein the first memory device has a first data storage capacity; and the second memory device has a second data storage capacity. The pin configuration of the multi-memory architecture is compatible with the first memory device with the externally accessible data storage capacity, wherein the externally-accessible data storage capacity can be either the first data storage capacity, the second data storage capacity, or the sum of the first and second data storage capacties.

Abstract: A double protection virtual ground memory circuit and column decoder. Through the introduction of a double protection circuit, leakage current from the virtual ground memory is reduced and power consumed by the memory circuit is lowered. Ultimately, sensing range of data within the memory by a sense amplifier is improved.