Abstract: Panel level methods and systems for packaging integrated circuits are described. In a method aspect of the invention, a substrate formed from a sacrificial semiconductor wafer is provided having a plurality of metallized device areas patterned thereon. Each device area includes an array of metallized contacts and a die attach area. Dice are mounted onto each device area and electrically connected to the array of contacts. The entire surface of the substrate including the dice, contacts and electrical connections is then encapsulated. The semiconductor wafer is then sacrificed leaving portions of the contacts exposed allowing the contacts to be used as external contacts in an IC package. In various embodiments, other structures, including die attach pads, may be incorporated into the device areas as desired. By way of example, structures having thicknesses in the range of 10 to 20 microns are readily attainable.

Abstract: An IC package and methods for making the same are described. The IC package includes a die and a heat sink that is attached to the back surface of the die with a thermal interface material layer. The heat sink includes a base and a partition. The partition extends around the periphery of the base and is offset from the outer edge of the base such that a ledge region is formed that surrounds the periphery of the base. The inner surfaces of the partition define an inner region that includes heat dissipation structures. A molding material encapsulates at least portions of the die and the ledge region around the periphery of the heat sink while leaving the inner region of the heat sink unencapsulated by molding material and exposed. The molding material covering the ledge region provides a locking feature that secures the heat sink in the package.

Abstract: Panel level methods and arrangements are described for attaching heat sinks in panel form with dice attached to a leadframe panel. Various methods produce integrated circuit packages each having an exposed heat sink on one outer surface of the package and an exposed die attach pad on a second opposite surface of the package.

Abstract: The present invention relates to methods and arrangements for forming a low stress cavity package. Particular methods may be performed with existing packaging equipment. In one such method, a leadframe laminated with adhesive film is provided. Integrated circuit dice are connected to the leadframe by reflowing solder between bond pads on the active surface of each die and the leadframe. A viscous thermosetting material is dispensed around the periphery of the active surface of each die. The thermosetting material fills gaps between the solder joint connections and the adhesive film. As a result, the thermosetting material, solder joint connections, each integrated circuit die and the adhesive film define and seal a protective cavity between the active surface of the die and the adhesive film. Portions of each die, leads, solder joint connections and adhesive film are encapsulated with a molding material that is prevented from entering the sealed cavity.

Abstract: Panel level methods and systems for packaging integrated circuits are described. In a method aspect of the invention, a substrate formed from a sacrificial semiconductor wafer is provided having a plurality of metallized device areas patterned thereon. Each device area includes an array of metallized contacts. Dice are mounted onto each device area and electrically connected to the array of contacts. The surface of the substrate including the dice, contacts and electrical connections is then encapsulated. The semiconductor wafer is then sacrificed leaving portions of the contacts exposed allowing the contacts to be used as external contacts in an IC package. In various embodiments, other structures, including saw street structures, may be incorporated into the device areas as desired. By way of example, structures having thicknesses in the range of 10 to 20 microns are readily attainable.

Abstract: Panel level methods and systems for packaging integrated circuits are described. In a method aspect of the invention, a substrate formed from a sacrificial semiconductor wafer is provided having a plurality of metallized device areas patterned thereon. Each device area includes an array of metallized contacts. Dice are mounted onto each device area and electrically connected to the array of contacts. The surface of the substrate including the dice, contacts and electrical connections is then encapsulated. The semiconductor wafer is then sacrificed leaving portions of the contacts exposed allowing the contacts to be used as external contacts in an IC package. In various embodiments, other structures, including saw street structures, may be incorporated into the device areas as desired. By way of example, structures having thicknesses in the range of 10 to 20 microns are readily attainable.

Abstract: Panel level methods and systems for packaging integrated circuits are described. In a method aspect of the invention, a substrate formed from a sacrificial semiconductor wafer is provided having a plurality of metallized device areas patterned thereon. Each device area includes an array of metallized contacts. Dice are mounted onto each device area and electrically connected to the array of contacts. The surface of the substrate including the dice, contacts and electrical connections is then encapsulated. The semiconductor wafer is then sacrificed leaving portions of the contacts exposed allowing the contacts to be used as external contacts in an IC package. In various embodiments, other structures, including saw street structures, may be incorporated into the device areas as desired. By way of example, structures having thicknesses in the range of 10 to 20 microns are readily attainable.

Abstract: The present invention relates to methods and arrangements for forming a low stress cavity package. Particular methods may be performed with existing packaging equipment. In one such method, a leadframe laminated with adhesive film is provided. Integrated circuit dice are connected to the leadframe by reflowing solder between bond pads on the active surface of each die and the leadframe. A viscous thermosetting material is dispensed around the periphery of the active surface of each die. The thermosetting material fills gaps between the solder joint connections and the adhesive film. As a result, the thermosetting material, solder joint connections, each integrated circuit die and the adhesive film define and seal a protective cavity between the active surface of the die and the adhesive film. Portions of each die, leads, solder joint connections and adhesive film are encapsulated with a molding material that is prevented from entering the sealed cavity.

Abstract: Apparatuses and methods directed to a semiconductor chip package having an optical component are disclosed. Packages include a die having a light sensing region and a stress buffer on a first surface, a first opaque encapsulant having an opening therethrough disposed atop the first surface, and a second transparent or translucent encapsulant formed within the first encapsulant opening and directly atop and contacting the light sensing region. A leadless leadframe or other conductive component can be coupled to a second surface of the die. The die may also have light sensitive regions that are shielded by the first encapsulant and/or stress buffer. The stress buffer can be a layer formed at the wafer stage or a dam formed at the panel stage. A customized mold is used while dispensing the first encapsulant such that the opening therethrough is properly formed.

Abstract: Apparatuses and methods directed to a semiconductor chip package having an optical component are disclosed. Packages include a die having a light sensing region and a stress buffer on a first surface, a first opaque encapsulant having an opening therethrough disposed atop the first surface, and a second transparent or translucent encapsulant formed within the first encapsulant opening and directly atop and contacting the light sensing region. A leadless leadframe or other conductive component can be coupled to a second surface of the die. The die may also have light sensitive regions that are shielded by the first encapsulant and/or stress buffer. The stress buffer can be a layer formed at the wafer stage or a dam formed at the panel stage. A customized mold is used while dispensing the first encapsulant such that the opening therethrough is properly formed.

Abstract: Panel level methods and arrangements are described for attaching heat sinks in panel form with dice attached to a leadframe panel. Various methods produce integrated circuit packages each having an exposed heat sink on one outer surface of the package and an exposed die attach pad on a second opposite surface of the package.

Abstract: Panel level methods and systems for packaging integrated circuits are described. In a method aspect of the invention, a substrate formed from a sacrificial semiconductor wafer is provided having a plurality of metallized device areas patterned thereon. Each device area includes an array of metallized contacts. Dice are mounted onto each device area and electrically connected to the array of contacts. The surface of the substrate including the dice, contacts and electrical connections is then encapsulated. The semiconductor wafer is then sacrificed leaving portions of the contacts exposed allowing the contacts to be used as external contacts in an IC package. In various embodiments, other structures, including saw street structures, may be incorporated into the device areas as desired. By way of example, structures having thicknesses in the range of 10 to 20 microns are readily attainable.

Abstract: An IC package and methods for making the same are described. The IC package includes a die and a heat sink that is attached to the back surface of the die with a thermal interface material layer. The heat sink includes a base and a partition. The partition extends around the periphery of the base and is offset from the outer edge of the base such that a ledge region is formed that surrounds the periphery of the base. The inner surfaces of the partition define an inner region that includes heat dissipation structures. A molding material encapsulates at least portions of the die and the ledge region around the periphery of the heat sink while leaving the inner region of the heat sink unencapsulated by molding material and exposed. The molding material covering the ledge region provides a locking feature that secures the heat sink in the package.

Abstract: A method for forming integral heat sinks on back surfaces of integrated circuit devices at wafer level is described. A first metallic layer is deposited over the back surface of a wafer. A second metallic layer is deposited over the first metallic layer. Optionally, a third metallic layer is deposited over the second metallic layer. The first metallic layer, the second metallic layer, and optionally the third metallic layer form the integral heat sink for the wafer. When the wafer is diced into multiple semiconductor devices, each semiconductor device has an integral heat sink formed on its back surface that includes the first metallic layer, the second metallic layer, and optionally the third metallic layer. Optionally, each semiconductor device is connected to a lead frame via solder bumps or bonding wires to form an integrated circuit (IC) package.