Patents by Inventor Sheela R. Shreedharan

Sheela R. Shreedharan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Reduced power set-reset latch based flip-flop
    Patent number: 10033356
    Abstract: An apparatus includes a master latch circuit including a first circuit and a second circuit, and a slave latch circuit including a third circuit and a fourth circuit. The first circuit and the second circuit may be coupled to a first shared circuit node, and the third circuit and the fourth circuit may be coupled to a second shared circuit node. The master latch circuit may be configured to store a value of an input signal in response to an assertion of a clock signal. The slave latch circuit may be configured to store an output value of the master latch circuit in response to a de-assertion of the clock signal. The master latch circuit may also be configured to de-couple the first shared circuit node from a ground reference node in response to the de-assertion of the clock signal.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: July 24, 2018
    Assignee: Apple Inc.
    Inventors: Zhao Wang, Sheela R. Shreedharan, Ajay Kumar Bhatia, Michael R. Seningen
  • REDUCED POWER SET-RESET LATCH BASED FLIP-FLOP
    Publication number: 20170366170
    Abstract: An apparatus includes a master latch circuit including a first circuit and a second circuit, and a slave latch circuit including a third circuit and a fourth circuit. The first circuit and the second circuit may be coupled to a first shared circuit node, and the third circuit and the fourth circuit may be coupled to a second shared circuit node. The master latch circuit may be configured to store a value of an input signal in response to an assertion of a clock signal. The slave latch circuit may be configured to store an output value of the master latch circuit in response to a de-assertion of the clock signal. The master latch circuit may also be configured to de-couple the first shared circuit node from a ground reference node in response to the de-assertion of the clock signal.
    Type: Application
    Filed: November 18, 2016
    Publication date: December 21, 2017
    Inventors: Zhao Wang, Sheela R. Shreedharan, Ajay Kumar Bhatia, Michael R. Seningen