Patents by Inventor Sheetal Jain

Sheetal Jain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10685925
    Abstract: Systems and methods that facilitate resistance and capacitance balancing are presented. In one embodiment, a system comprises: a plurality of ground lines configured to ground components; and a plurality of signal bus lines interleaved with the plurality of ground lines, wherein the interleaving is configured so that plurality of signal bus lines and plurality of ground lines are substantially evenly spaced and the plurality of signal bus lines convey a respective plurality of signals have similar resistance and capacitance constants that are balanced. The plurality of signals can see a substantially equal amount ground surface and have similar amounts of capacitance. The plurality of signal bus lines can have similar cross sections and lengths with similar resistances. The plurality of signal bus lines interleaved with the plurality of ground lines can be included in a two copper layer interposer design with one redistribution layer (RDL).
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: June 16, 2020
    Assignee: NVIDIA CORPORATION
    Inventors: Jim Dobbins, Sheetal Jain, Don Templeton, Yaping Zhou, Wenjun Shi, Sunil Sudhakaran
  • Patent number: 10600730
    Abstract: In one embodiment, a system comprises: a plurality of aggressor bus lines; and a plurality of differential pair bus lines that are located in relatively parallel close proximity to the plurality of aggressor bus lines, wherein at least two of the plurality of differential pair bus lines change location with respect to each other at a point that has a cancelling affect on cross talk from the plurality of aggressor bus lines, wherein the change includes cross over routing. The plurality of differential pair bus lines can convey differential clock signals. The routing of the plurality of differential pair bus lines is substantially parallel to one another before and after the change.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: March 24, 2020
    Assignee: NVIDIA CORPORATION
    Inventors: Jim Dobbins, Sheetal Jain, Don Templeton, Yaping Zhou, Wenjun Shi, Sunil Sudhakaran
  • Publication number: 20190237399
    Abstract: In one embodiment, a system comprises: a plurality of aggressor bus lines; and a plurality of differential pair bus lines that are located in relatively parallel close proximity to the plurality of aggressor bus lines, wherein at least two of the plurality of differential pair bus lines change location with respect to each other at a point that has a cancelling affect on cross talk from the plurality of aggressor bus lines, wherein the change includes cross over routing. The plurality of differential pair bus lines can convey differential clock signals. The routing of the plurality of differential pair bus lines is substantially parallel to one another before and after the change.
    Type: Application
    Filed: January 26, 2018
    Publication date: August 1, 2019
    Inventors: Jim Dobbins, Sheetal Jain, Don Templeton, Yaping Zhou, Wenjun Shi, Sunil Sudhakaran
  • Publication number: 20190237417
    Abstract: Systems and methods that facilitate resistance and capacitance balancing are presented. In one embodiment, a system comprises: a plurality of ground lines configured to ground components; and a plurality of signal bus lines interleaved with the plurality of ground lines, wherein the interleaving is configured so that plurality of signal bus lines and plurality of ground lines are substantially evenly spaced and the plurality of signal bus lines convey a respective plurality of signals have similar resistance and capacitance constants that are balanced. The plurality of signals can see a substantially equal amount ground surface and have similar amounts of capacitance. The plurality of signal bus lines can have similar cross sections and lengths with similar resistances. The plurality of signal bus lines interleaved with the plurality of ground lines can be included in a two copper layer interposer design with one redistribution layer (RDL).
    Type: Application
    Filed: January 26, 2018
    Publication date: August 1, 2019
    Inventors: Jim Dobbins, Sheetal Jain, Don Templeton, Yaping Zhou, Wenjun Shi, Sunil Sudhakaran
  • Publication number: 20080068512
    Abstract: A digital radio frequency (RF) modulator provides modulation for base-band TV signals. The RF modulator provides direct conversion of digital base-band audio and video signals to a desired RF channel frequency, without any analog up conversion. The RF modulator includes an audio module, a video module, and a RF converter. The audio module includes a pre-emphasis filter, a multi-stage audio interpolator and a complex frequency modulator to generate frequency modulated (FM) audio signals. The video module includes a complex VSB filter, a group-delay compensation filter and some processing logic to generate a filtered output video signal. The RF converter includes a complex adder, a complex multiplier and a RF interpolator to construct the base band TV signals and to shift the base band TV signals in a frequency domain to the desired RF channel frequency. The exponential video carrier is generated at baseband and has a frequency whose value is in the range of +/? 13.5 MHz.
    Type: Application
    Filed: August 20, 2007
    Publication date: March 20, 2008
    Applicant: STMicroelectronics PVT. LTD.
    Inventors: Vivek Sharma, Sheetal Jain
  • Publication number: 20070180411
    Abstract: A method and an apparatus are provided for comparing a first semiconductor-related technical system with a second semiconductor-related technical system using statistical means. First statistical data characterizing the first technical system and second statistical data characterizing the second technical system are provided. A statistical test comparing the first statistical data with the second statistical data is performed after the first and second statistical data has been provided. Whether the first and second technical system are equivalent is then determined depending on the result of the statistical test.
    Type: Application
    Filed: January 27, 2006
    Publication date: August 2, 2007
    Inventors: Wolfgang Swegat, Sheetal Jain, Ankur Gupta