Abstract: The present embodiments relate to a PMR write-head structure where the spin-orbit torque (SOT) material is in contact with the main pole in the write gap (WG). In addition, with the write shield (WS) electrically isolated from the side shield (SS) in the present designs, the current can be confined in the SOT material near the main pole, and the device resistance can remain within a reasonable range. It can be shown, using simulations, that the main pole switching rise time can be improved by 18˜24% using spin-orbit torque from heavy metals like platinum.

Abstract: The present embodiments relate to a write head design with a patterned hot seed (HS). Particularly, the HS can be patterned as part of a multi-step patterning process that can partially or completely remove portions of the HS at multiple sides to form various designs. For example, the HS can have a two-step cliff design, etching multiple steps around an un-patterned center portion, and a flared angle. The designs of the patterned HS can improve write head performance.

Abstract: The present embodiments can generally provide a magnetic write head structure with optimized gap current distribution to maximize the current-assisted areal density capacity (ADC) gain in hard-disk-drive storage devices. In a first example embodiment, a non-dual-write-shield (nDWS) write head can include a main pole (MP), a trailing shield (TS), and a write gap (WG) disposed between the MP and the TS. The write head can also include a side shield (SS), a leading shield (LS), and a write shield (WS). The write head can include a side gap (SG) between the MP and the SS on both sides of the MP tip, and a leading gap (LG) between the MP and the LS. The write head can also include a coil wrapped around the MP through a PP3 shield that is configured to direct a time-dependent write current to saturate magnetization of the MP.

Abstract: A rectifier device, has a Hall layer comprising a layer of a Hall material, and a spin-orbit layer adjacent the Hall layer. The spin-orbit layer has a spin-orbit material having a first surface and a second surface, a ferromagnet adjacent the spin-orbit material, and oxide on the outer surfaces of the spin-orbit layer. A rectifying system has an array of the above rectifying devices having a number, K, of parallel branches, each branch having N devices, branch electrical connections between corresponding devices in each of the parallel branches, and device electrical connection between devices in each parallel branch.

Abstract: The present embodiments can generally provide a magnetic write head structure with optimized gap current distribution to maximize the current-assisted areal density capacity (ADC) gain in hard-disk-drive storage devices. In a first example embodiment, a non-dual-write-shield (nDWS) write head can include a main pole (MP), a trailing shield (TS), and a write gap (WG) disposed between the MP and the TS. The write head can also include a side shield (SS), a leading shield (LS), and a write shield (WS). The write head can include a side gap (SG) between the MP and the SS on both sides of the MP tip, and a leading gap (LG) between the MP and the LS. The write head can also include a coil wrapped around the MP through a PP3 shield that is configured to direct a time-dependent write current to saturate magnetization of the MP.

Abstract: The present disclosure relates to a magnetic memory structure with a voltage-controlled gain-cell configuration, which includes a memory resistive device, a first transistor connected in series with the memory resistive device, and a second transistor. The memory resistive device has a baseline resistance larger than 10 M?, and is eligible to exhibit a ‘1’ state and a ‘0’ state and exhibit a resistance change between the ‘1’ state and the ‘0’ state. The second transistor has a gate connected to a connection node of the first transistor and the memory resistive device. When the memory resistive device exhibits the ‘1’ state, a gate voltage for the second transistor is smaller than a threshold voltage of the second transistor, and when the memory resistive device exhibits the ‘0’ state, the gate voltage for the second transistor is larger than the threshold voltage of the second transistor.

Abstract: The present disclosure relates to a magnetic memory structure with a voltage-controlled gain-cell configuration, which includes a memory resistive device, a first transistor connected in series with the memory resistive device, and a second transistor. The memory resistive device has a baseline resistance larger than 10 M?, and is eligible to exhibit a ‘1’ state and a ‘0’ state and exhibit a resistance change between the ‘1’ state and the ‘0’ state. The second transistor has a gate connected to a connection node of the first transistor and the memory resistive device. When the memory resistive device exhibits the ‘1’ state, a gate voltage for the second transistor is smaller than a threshold voltage of the second transistor, and when the memory resistive device exhibits the ‘0’ state, the gate voltage for the second transistor is larger than the threshold voltage of the second transistor.

Abstract: A switching device is disclosed. The switching device includes a spin-orbit coupling (SOC) layer, a pure spin conductor (PSC) layer disposed atop the SOC layer, a ferromagnetic (FM) layer disposed atop the PSC layer, and a normal metal (NM) layer sandwiched between the PSC layer and the FM layer. The PSC layer is a ferromagnetic insulator (FMI) is configured to funnel spins from the SOC layer onto the NM layer and to further provide a charge insulation so as to substantially eliminate current shunting from the SOC layer while allowing spins to pass through. The NM layer is configured to funnel spins from the PSC layer into the FM layer.

Abstract: A magnetic memory structure employs electric-field controlled interlayer exchange coupling between a free magnetic layer and a fixed magnetic layer to switch a magnetization direction. The magnetic layers are separated by a spacer layer disposed between two oxide layers. The spacer layer exhibits a large IEC while the oxide layers provide tunnel barriers, forming a quantum-well between the magnetic layers with discrete energy states above the equilibrium Fermi level. When an electric field is applied across the structure, the tunnel barriers become transparent at discrete energy states via a resonant tunneling phenomenon. The wave functions of the two magnets then can interact and interfere to provide a sizable IEC. IEC can control the magnetization direction of the free magnetic layer relative to the magnetization direction of the fixed magnetic layer depending on the sign of the IEC, induced by a magnitude of the applied electric field above a threshold value.

Abstract: A magnetic memory structure employs electric-field controlled interlayer exchange coupling between a free magnetic layer and a fixed magnetic layer to switch a magnetization direction. The magnetic layers are separated by a spacer layer disposed between two oxide layers. The spacer layer exhibits a large IEC while the oxide layers provide tunnel barriers, forming a quantum-well between the magnetic layers with discrete energy states above the equilibrium Fermi level. When an electric field is applied across the structure, the tunnel barriers become transparent at discrete energy states via a resonant tunneling phenomenon. The wave functions of the two magnets then can interact and interfere to provide a sizable IEC. IEC can control the magnetization direction of the free magnetic layer relative to the magnetization direction of the fixed magnetic layer depending on the sign of the IEC, induced by a magnitude of the applied electric field above a threshold value.

Abstract: A switching device is disclosed. The switching device includes a spin-orbit coupling (SOC) layer, a pure spin conductor (PSC) layer disposed atop the SOC layer, a ferromagnetic (FM) layer disposed atop the PSC layer, and a normal metal (NM) layer sandwiched between the PSC layer and the FM layer. The PSC layer is a ferromagnetic insulator (FMI) is configured to funnel spins from the SOC layer onto the NM layer and to further provide a charge insulation so as to substantially eliminate current shunting from the SOC layer while allowing spins to pass through. The NM layer is configured to funnel spins from the PSC layer into the FM layer.

Abstract: A switching device is disclosed. The switching device includes a spin-orbit coupling (SOC) layer, a pure spin conductor (PSC) layer disposed atop the SOC layer, a ferromagnetic (FM) layer disposed atop the PSC layer, and a normal metal (NM) layer sandwiched between the PSC layer and the FM layer. The PSC layer is a ferromagnetic insulator (FMI) is configured to funnel spins from the SOC layer onto the NM layer and to further provide a charge insulation so as to substantially eliminate current shunting from the SOC layer while allowing spins to pass through. The NM layer is configured to funnel spins from the PSC layer into the FM layer.

Abstract: A spintronic memory device having a spin momentum-locking (SML) channel, a nanomagnet structure (NMS) disposed on the SML, and a plurality of normal metal electrodes disposed on the SML. The magnetization orientation of the NMS is controlled by current injection into the SML through normal metal electrode. The magnetization orientation of the NMS is determined by measuring voltages across the NMS and the SML while flowing charge current through the SML via the normal metal electrodes.

Abstract: A spintronic memory device having a spin momentum-locking (SML) channel, a nanomagnet structure (NMS) disposed on the SML, and a plurality of normal metal electrodes disposed on the SML. The magnetization orientation of the NMS is controlled by current injection into the SML through normal metal electrode. The magnetization orientation of the NMS is determined by measuring voltages across the NMS and the SML while flowing charge current through the SML via the normal metal electrodes.

Abstract: A switching device is disclosed. The switching device includes a spin-orbit coupling (SOC) layer, a pure spin conductor (PSC) layer disposed atop the SOC layer, a ferromagnetic (FM) layer disposed atop the PSC layer, and a normal metal (NM) layer sandwiched between the PSC layer and the FM layer. The PSC layer is a ferromagnetic insulator (FMI) is configured to funnel spins from the SOC layer onto the NM layer and to further provide a charge insulation so as to substantially eliminate current shunting from the SOC layer while allowing spins to pass through. The NM layer is configured to funnel spins from the PSC layer into the FM layer.