Patents by Inventor Shei Meng LOO

Shei Meng LOO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260206608
    Abstract: A wafer includes integrated circuit areas, where each integrated circuit area has at least one conductive die pad. A passivation layer is provided over the conductive die pads. A die pad opening is formed extending through the passivation layer at each die pad. Use a jet printing process, a dot of conductive ink is deposited at each die pad opening to form a die pad protection layer covering an upper surface of each conductive die pad. A film layer covers the passivation layer and the die pad protection layer at each die pad. Using a laser drilling process, a via opening if formed extending through the film layer at each die pad to reach the die pad protection layer. The die pad protection layer protects the die pad during the laser drilling.
    Type: Application
    Filed: December 4, 2025
    Publication date: July 16, 2026
    Applicant: STMicroelectronics International N.V.
    Inventors: Shei Meng LOO, David GANI
  • Publication number: 20240429095
    Abstract: A method of relocation of input/output (I/O) contact pads in a wafer-level package is provided. A method of manufacturing a wafer-level package can include: forming a redistribution layer on a wafer having a contact pad disposed thereon, where the wafer defines a plane along a major horizontal surface on which the contact pad is disposed; drilling, with a multi-axis laser drill, a hole along an axis through the redistribution layer to reach the contact pad, where the axis of the hole through the redistribution layer is at an angle relative to the plane that is neither parallel nor orthogonal; and forming a contact extending from the contact pad, through the hole through the redistribution layer, to a position on the redistribution layer.
    Type: Application
    Filed: June 4, 2024
    Publication date: December 26, 2024
    Inventor: Shei Meng LOO
  • Publication number: 20240297147
    Abstract: A hybrid QFN and QFP integrated circuit package includes a leadframe with first second die pads supporting first and second integrated circuits, respectively. The leadframe further includes QFN conductive pads QFP conductive leads. A package housing encapsulates the first and second die pads, the first and second integrated circuits mounted thereto, the QFN conductive pads, and proximal ends of the QFP conductive leads. Distal ends of the QFP conductive leads extend away from side edges of the package housing. Bottom surfaces of the QFN conductive pads are exposed at a bottom surface of the package housing. The QFN conductive pads are located between the first and second die pads.
    Type: Application
    Filed: February 14, 2024
    Publication date: September 5, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Shei Meng LOO, Edsel DE JESUS