Abstract: A critical-path timing sensor detects set-up timing failures from a functional critical path to a path flip-flop. The functional critical path carries test data during test mode, and normal data during normal device operation. The path flip-flop's D input and Q output are compared by an exclusive-OR (XOR) gate and sampled by an early capture flip-flop that is clocked by a delayed clock, sampling D and Q just after the path flip-flop is clocked. When set-up time fails, D and Q differ just after the clock edge and a timing failure is latched. Timing failures activate a controller to increase VDD, while VDD is reduced in the absence of timing failures. Process variations are accounted for, allowing for lower power or faster operation. A margin delay between the functional critical path end and the early capture flip-flop detects timing failures before they occur in the path flip-flop.