Abstract: Provided are methods of manufacturing comprising providing a FET base structure, the FET base structure comprising a substrate, a drain and a source; and providing a channel layer on the FET base structure; and providing a first layer on the FET base structure. The first layer comprises a one-dimensional or two-dimensional material and is arranged on an upper surface of the channel layer so as to form a sensing surface of the FET. The step of providing the channel layer comprises forming the channel layer and subsequently transferring the channel layer onto the FET base structure. Alternatively or additionally, the step of providing the first layer on the FET base structure comprises forming the first layer and subsequently transferring the first layer onto the FET base structure.

Abstract: Provided are methods of manufacturing comprising providing a FET base structure, the FET base structure comprising a substrate, a drain and a source; and providing a channel layer on the FET base structure; and providing a first layer on the FET base structure. The first layer comprises a one-dimensional or two-dimensional material and is arranged on an upper surface of the channel layer so as to form a sensing surface of the FET. The step of providing the channel layer comprises forming the channel layer and subsequently transferring the channel layer onto the FET base structure. Alternatively or additionally, the step of providing the first layer on the FET base structure comprises forming the first layer and subsequently transferring the first layer onto the FET base structure.

Abstract: Provided are methods of manufacturing comprising providing a FET base structure, the FET base structure comprising a substrate, a drain and a source; and providing a channel layer on the FET base structure; and providing a first layer on the FET base structure. The first layer comprises a one-dimensional or two-dimensional material and is arranged on an upper surface of the channel layer so as to form a sensing surface of the FET. The step of providing the channel layer comprises forming the channel layer and subsequently transferring the channel layer onto the FET base structure. Alternatively or additionally, the step of providing the first layer on the FET base structure comprises forming the first layer and subsequently transferring the first layer onto the FET base structure.

Abstract: A scan of F. tularensis genome for homology to a regulatory protein that controls virulence identified gene FTL0552. A knock out mutation in FTL0552 was created using reverse transcriptase PCR and the construct inserted into F. tularensis. This mutant was defective for survival in macrophages and found avirulent in in vivo testing, where the mutant exhibited reduced levels of pro-inflammatory cytokine production, reduced evidence of histopathology in affected tissues, reduced systemic infection, and rapid clearance of the bacterium. In vivo challenge studies with the FTL0552 mutant using the virulent F. tularensis subsp. tularensis SchuS4 strain show an immune response is induced, and protection afforded, after preexposure to the FTL0552 mutant. Microarray studies revealed 148 genes regulated by FTL0552, including genes located within the FPI that are essential for intracellular survival.