Abstract: An apparatus includes a processor circuit that includes a memory circuit, one or more processor cores, and a debug circuit. The debug circuit may be configured, in response to activation of a trace mode to record information indicative of instructions executing on the one or more processor cores, to write a trace data stream to the memory circuit that includes trace data collected on the instructions executing on the one or more processor cores. In response to a particular instruction within one of the processor cores specifying a write of a data value to an architecturally visible trace register, the debug circuit may be further configured to output the data value to the trace data stream as part of executing the particular instruction.

Abstract: Systems and methods for predicting an indirect branch target address. A strided target address predictor (STAP) system can observe a striding pattern from a previous indirect branch target. The system can predict a target address based on the observed striding pattern. The system can initialize a confidence counter. The system can determine a previous indirect branch target address. The system can determine a predicted target address.