Patents by Inventor Shekoufeh Qawami

Shekoufeh Qawami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220004329
    Abstract: Methods, systems, and devices for operating a memory array are described. A memory controller may be configured to provide enhanced bandwidth on a command/address (C/A) bus, which may have a relatively low pin count, through use of a next partition command that may repeat an array command from a current partition at a different partition indicated by the next partition command. Such a next partition command may use fewer clock cycles than a command that includes a complete instruction and memory location information.
    Type: Application
    Filed: July 15, 2021
    Publication date: January 6, 2022
    Inventors: Shekoufeh Qawami, Rajesh Sundaram
  • Patent number: 11200113
    Abstract: A memory device has multiple nonvolatile (NV) memory arrays that collectively store a block of data, with each array to store a portion of the data block. A selected NV memory array stores a write count for the block of data. In response to a write command, the NV memory arrays that store data perform an internal pre-write read. The selected NV memory array that stores the write count will perform a pre-write read of the write count, increment the write count internally to the selected NV memory array, and write the incremented write count back to the selected NV memory array.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: December 14, 2021
    Assignee: Intel Corporation
    Inventor: Shekoufeh Qawami
  • Patent number: 11194472
    Abstract: Techniques to update a trim parameter in non-volatile memory during either a manufacturing stage or a post-manufacturing stage are described. Trim parameters may be stored in a register located within the memory device that is inaccessible by a host device during a normal mode of operation. Post-manufacturing updates to trim parameters by the host device may be feasible by creating registers located within the memory device that are accessible to the host device to provide information regarding trim parameter setting updates. The memory device may read the information from the registers accessible to the host device to update trim parameters stored in the register inaccessible by the host device. In this manner, the host device may not have a direct access to the trim parameters but still be able to provide an update to the trim parameters by updating an entry of the registers accessible by the host device.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: December 7, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Shekoufeh Qawami, Doyle W. Rivers
  • Patent number: 11188264
    Abstract: A memory system includes a nonvolatile (NV) memory device with asymmetry between intrinsic read operation delay and intrinsic write operation delay. The system can select to perform memory access operations with the NV memory device with the asymmetry, in which case write operations have a lower delay than read operations. The system can alternatively select to perform memory access operations with the NV memory device where a configured write operation delay that matches the read operation delay.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: November 30, 2021
    Assignee: Intel Corporation
    Inventors: Shekoufeh Qawami, Philip Hillier, Benjamin Graniello, Rajesh Sundaram
  • Patent number: 11145369
    Abstract: According to one embodiment of the present invention, an apparatus is disclosed. The apparatus includes a memory array having a plurality of memory cells. The apparatus further includes memory access circuits coupled to the memory array and configured to perform write operations responsive to control signals. The apparatus further includes control logic coupled to the memory access circuits and configured to apply a set of write parameters based, at least in part, on a number of write operations performed by the memory access circuits and further configured to provide control signals to the memory access circuits to perform write operations on the plurality of memory cells according to the set of write parameters.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: October 12, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Shekoufeh Qawami, Rajesh Sundaram
  • Patent number: 11068183
    Abstract: Methods, systems, and devices for operating a memory array are described. A memory controller may be configured to provide enhanced bandwidth on a command/address (C/A) bus, which may have a relatively low pin count, through use of a next partition command that may repeat an array command from a current partition at a different partition indicated by the next partition command. Such a next partition command may use fewer clock cycles than a command that includes a complete instruction and memory location information.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: July 20, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Shekoufeh Qawami, Rajesh Sundaram
  • Patent number: 11010061
    Abstract: Cross point memory architectures, devices, systems, and methods are disclosed and described, and can include a cross point memory core subsystem having increased bandwidth that is scalable. The memory core can include a plurality of independently operating partitions, each comprising a plurality of cross point memory arrays.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: May 18, 2021
    Assignee: Intel Corporation
    Inventors: Rajesh Sundaram, Albert Fazio, Derchang Kau, Shekoufeh Qawami
  • Patent number: 10948915
    Abstract: Apparatuses, methods and storage medium associated with computer-assisted or autonomous vehicle incident management, are disclosed herein. In some embodiments, a vehicle incident management system includes a main system controller to determine whether a vehicle hosting the apparatus is involved in a vehicle incident; if so, whether another vehicle is involved; and if so, whether the other vehicle is equipped to exchange incident information; and an inter-vehicle communication subsystem to exchange incident information with the other vehicle, on determination that the vehicle is involved in a vehicle incident involving the other vehicle, and the other vehicle is equipped to exchange incident information. Other embodiments are also described and claimed.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: March 16, 2021
    Assignee: Intel Corporation
    Inventors: Shekoufeh Qawami, Casey Baron, Kooi Chi Ooi, Naissa Conde, Mengjie Yu
  • Patent number: 10942562
    Abstract: Methods and apparatus to manage operation of variable-state computing devices using artificial intelligence are disclosed. An example computing device includes a hardware platform. The example computing device also includes an artificial intelligence (AI) engine to: determine a context of the device; and adjust an operation of the hardware platform based on an expected change in the context of the device. The adjustment modifies at least one of a computational efficiency of the device, a power efficiency of the device, or a memory response time of the device.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: March 9, 2021
    Assignee: Intel Corporation
    Inventors: Shekoufeh Qawami, Nageen Himayat, Chaitanya Sreerama, Hassnaa Moustafa, Rita Wouhaybi, Linda Hurd, Nadine L Dabby, Van Le, Gayathri Jeganmohan, Ankitha Chandran
  • Patent number: 10936418
    Abstract: Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: March 2, 2021
    Assignee: Intel Corporation
    Inventors: Kiran Pangal, Prashant S. Damle, Rajesh Sundaram, Shekoufeh Qawami, Julie M. Walker, Doyle Rivers
  • Patent number: 10930365
    Abstract: In embodiments, a memory controller (MC) includes an output interface, and an execution engine (EE) to identify, based on field test results of a die coupled to the MC, initial test results of the die using an artificial neural network (ANN) trained to identify the die from a set of NVM dies based on initial test results of the set of NVM dies obtained at a time of manufacture of the set of dies. The initial test results include a first useful life prediction and the field test results include a second useful life prediction, and the initial test results are regenerated by the ANN to protect their confidentiality. In embodiments, the MC is further to compare the second useful life prediction with the first useful life prediction, to determine a deviation between the two, and output, via the output interface, the deviation to a user.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: February 23, 2021
    Assignee: Intel Corporation
    Inventors: Pavel Poliakov, Andrey Kudryavtsev, Shekoufeh Qawami, Amirali Khatib Zadeh, Monte Klinkenborg
  • Patent number: 10872647
    Abstract: A memory device performs DLL (delay locked loop) calibration in accordance with a DLL calibration mode configured for the memory device. A host controller can configure the calibration mode based on operating conditions for the memory device. The memory device includes an input/output (I/O) interface circuit and a delay locked loop (DLL) circuit coupled to control I/O timing of the I/O interface. A control circuit of the memory device selectively enables and disables DLL calibration in accordance with the DLL calibration mode. When selectively enabled, the DLL calibration is to operate at a time interval identified by the DLL calibration mode, and when selectively disabled, the DLL calibration is to cease or refrain from DLL calibration operations.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: December 22, 2020
    Assignee: Intel Corporation
    Inventors: Shekoufeh Qawami, Michael J. Allen, Rajesh Sundaram
  • Patent number: 10847245
    Abstract: A memory controller includes a memory to store results of a reference performance test (RT) performed on a non-volatile memory (NVM) die, where the results of the RT include one or more first indicators of failure associated with one or more first read/write cycles of the NVM die before the NVM die is placed in use. The memory controller further includes an analyzer coupled with the memory to perform, in one or more second read/write cycles, one or more field tests that provide second indicators of failure associated with one or more second read/write cycles of the NVM die during the use of the NVM die, and further to predict and dynamically adjust, over one or more second read/write cycles, at least one of likelihood or expected time of failure of the NVM, based at least in part on the first and second indicators of failure.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: Pavel Poliakov, Andrey Kudryavtsev, Shekoufeh Qawami, Amirali Khatib Zadeh
  • Publication number: 20200341635
    Abstract: Apparatuses and methods for performing multithread, concurrent access of different partition of a memory are disclosed herein. An example apparatus may include a non-volatile memory array comprising a plurality of partitions. Each of the plurality of partitions may include a respective plurality of memory cells. The apparatus may further include a plurality of local controllers that are each configured to independently and concurrently access a respective one of the plurality of partitions to execute a respective memory access command of a plurality of memory access commands responsive to receiving the respective memory access command. The example apparatus may further include a controller configured to receive the plurality of memory access commands and to determine a respective target partition of the plurality of partitions for each of the plurality of memory access commands.
    Type: Application
    Filed: July 10, 2020
    Publication date: October 29, 2020
    Applicant: Micron Technology, Inc.
    Inventors: RAJESH SUNDARAM, DERCHANG KAU, OWEN W. JUNGROTH, DANIEL CHU, RAYMOND W. ZENG, SHEKOUFEH QAWAMI
  • Patent number: 10817201
    Abstract: Examples of a multi-level memory with direct access are described. Examples include designating an amount of a non-volatile random access memory (NVRAM) for use as memory for a computer system. Examples also include designating a second amount of the NVRAM to for use as storage for the computing device. Examples also include re-designating at least a first portion of the first amount of NVRAM from use as memory to use as storage.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: October 27, 2020
    Assignee: Intel Corporation
    Inventors: Blaise Fanning, Shekoufeh Qawami, Raymond S. Tetrick, Frank T. Hady
  • Publication number: 20200241751
    Abstract: Techniques to update a trim parameter in non-volatile memory during either a manufacturing stage or a post-manufacturing stage are described. Trim parameters may be stored in a register located within the memory device that is inaccessible by a host device during a normal mode of operation. Post-manufacturing updates to trim parameters by the host device may be feasible by creating registers located within the memory device that are accessible to the host device to provide information regarding trim parameter setting updates. The memory device may read the information from the registers accessible to the host device to update trim parameters stored in the register inaccessible by the host device. In this manner, the host device may not have a direct access to the trim parameters but still be able to provide an update to the trim parameters by updating an entry of the registers accessible by the host device.
    Type: Application
    Filed: April 14, 2020
    Publication date: July 30, 2020
    Inventors: Shekoufeh Qawami, Doyle W. Rivers
  • Patent number: 10719237
    Abstract: Apparatuses and methods for performing multithread, concurrent access of different partition of a memory are disclosed herein. An example apparatus may include a non-volatile memory array comprising a plurality of partitions. Each of the plurality of partitions may include a respective plurality of memory cells. The apparatus may further include a plurality of local controllers that are each configured to independently and concurrently access a respective one of the plurality of partitions to execute a respective memory access command of a plurality of memory access commands responsive to receiving the respective memory access command. The example apparatus may further include a controller configured to receive the plurality of memory access commands and to determine a respective target partition of the plurality of partitions for each of the plurality of memory access commands.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: July 21, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Rajesh Sundaram, Derchang Kau, Owen W. Jungroth, Daniel Chu, Raymond W. Zeng, Shekoufeh Qawami
  • Publication number: 20200227116
    Abstract: According to one embodiment of the present invention, an apparatus is disclosed. The apparatus includes a memory array having a plurality of memory cells. The apparatus further includes memory access circuits coupled to the memory array and configured to perform write operations responsive to control signals. The apparatus further includes control logic coupled to the memory access circuits and configured to apply a set of write parameters based, at least in part, on a number of write operations performed by the memory access circuits and further configured to provide control signals to the memory access circuits to perform write operations on the plurality of memory cells according to the set of write parameters.
    Type: Application
    Filed: March 27, 2020
    Publication date: July 16, 2020
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Shekoufeh QAWAMI, Rajesh SUNDARAM
  • Publication number: 20200174705
    Abstract: A memory system includes a nonvolatile (NV) memory device with asymmetry between intrinsic read operation delay and intrinsic write operation delay. The system can select to perform memory access operations with the NV memory device with the asymmetry, in which case write operations have a lower delay than read operations. The system can alternatively select to perform memory access operations with the NV memory device where a configured write operation delay that matches the read operation delay.
    Type: Application
    Filed: February 3, 2020
    Publication date: June 4, 2020
    Inventors: Shekoufeh QAWAMI, Philip HILLIER, Benjamin GRANIELLO, Rajesh SUNDARAM
  • Publication number: 20200151052
    Abstract: A memory device has multiple nonvolatile (NV) memory arrays that collectively store a block of data, with each array to store a portion of the data block. A selected NV memory array stores a write count for the block of data. In response to a write command, the NV memory arrays that store data perform an internal pre-write read. The selected NV memory array that stores the write count will perform a pre-write read of the write count, increment the write count internally to the selected NV memory array, and write the incremented write count back to the selected NV memory array.
    Type: Application
    Filed: January 14, 2020
    Publication date: May 14, 2020
    Inventor: Shekoufeh QAWAMI