Abstract: A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.

Abstract: Techniques for determining an identifier for a volume of memory in a memory device of a computer system. In an embodiment, the memory device detects an indication of an initialization event of the computer system and receives command information after the detecting of the indication. In certain embodiments, the memory device stores an identifier value for association with the volume of memory, wherein the storing is based on whether the received command information specifies that the volume of memory is to be assigned an identifier.

Abstract: Some embodiments of the invention pertain to a memory system containing multiple memory devices, in which one or multiple ones of the memory devices may flexibly be selected at one time for a common operation to be performed by all the selected devices concurrently.

Abstract: A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.

Abstract: A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.

Abstract: A method and apparatus for configuring a memory device, such as a flash memory device, is herein described. Features/functional modules of a memory device, are selectable by a manufacturer, customer, or user. Instead of a manufacturer having to complete numerous redesigns of a memory product to meet multiple customer's special needs, a single all inclusive device is manufactured and the customized features are selected/configured, by the manufacturer, or by the customer themselves. By using one time programmable (OTP) flags, the features are enabled or disabled, by the manufacturer, customer, or user, and may potentially not be altered by a user later. Moreover, after configuring a memory device, a manufacturer, customer, or end user may also lock down a configuration module to ensure the configuration itself is not later intentionally or inadvertently altered.

Abstract: A nonvolatile storage or memory device is accessed over a memory bus. The memory bus has an electrical interface typically used for volatile memory devices. A controller coupled to the bus sends synchronous data access commands to the nonvolatile memory device, and reads the response from the device bus based on an expected timing of a reply from the nonvolatile memory device. The controller determines the expected timing based on when the command was sent, and characteristics of the nonvolatile memory device. The controller may not need all the electrical signal lines available on the memory bus, and could issue data access commands to different groups of nonvolatile memory devices over different groups of electrical signal lines. The memory bus may be available and configured for either use with a memory controller and volatile memory devices, or a storage controller and nonvolatile memory devices.

Abstract: A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.

Abstract: Some embodiments of the invention pertain to a memory system containing multiple memory devices, in which one or multiple ones of the memory devices may flexibly be selected at one time for a common operation to be performed by all the selected devices concurrently.

Abstract: Some embodiments of the invention pertain to a memory system containing multiple memory devices, in which one or multiple ones of the memory devices may flexibly be selected at one time for a common operation to be performed by all the selected devices concurrently.

Abstract: Writing to non-volatile memory during a volatile memory refresh cycle is described. In one example, a write command is received and data is received to write into a memory cell. The data is temporarily stored in response to the write command. A refresh command is received and the temporarily stored data is written into the memory cell in response to the refresh command.

Abstract: Subject matter disclosed herein relates to management of a memory device.

Abstract: Some embodiments of the invention use a command-based interface to control reads and writes with non-volatile memory devices. This may reduce the number of pins that are needed on each integrated circuit, and therefore reduce the cost and size of those integrated circuits. In some embodiments, an on-die cache buffer may be used to buffer data transfers between a high-speed memory bus and the slower speed non-volatile array.

Abstract: In some types of non-volatile memory devices, the same signal from a memory device may be used for two purposes: During a read operation, the signal may be used by a memory controller to latch the data that is being received from the memory device. During a block erase operation and/or a block write operation, the signal may be used to notify the memory controller that the operation has been completed by the memory device.

Abstract: In various embodiments, a plurality of non-volatile memory devices, such as NAND flash memory device, may be connected to a host controller device in a fanned out configuration that allows each of the plurality of memory devices to perform read and/or write operations simultaneously. Each non-volatile memory device may include high speed input circuitry and high speed output circuitry so that transfers to and from memory are not limited by the speed of the flash memory read/write interface.

Abstract: In some types of non-volatile memory devices, the same signal from a memory device may be used for two purposes: During a read operation, the signal may be used by a memory controller to latch the data that is being received from the memory device. During a block erase operation and/or a block write operation, the signal may be used to notify the memory controller that the operation has been completed by the memory device.

Abstract: In various embodiments, a plurality of non-volatile memory devices, such as NAND flash memory device, may be connected to a host controller device in a fanned out configuration that allows each of the plurality of memory devices to perform read and/or write operations simultaneously. Each non-volatile memory device may include high speed input circuitry and high speed output circuitry so that transfers to and from memory are not limited by the speed of the flash memory read/write interface.

Abstract: Some embodiments of the invention use a command-based interface to control reads and writes with non-volatile memory devices. This may reduce the number of pins that are needed on each integrated circuit, and therefore reduce the cost and size of those integrated circuits. In some embodiments, an on-die cache buffer may be used to buffer data transfers between a high-speed memory bus and the slower speed non-volatile array.

Abstract: Some embodiments of the invention pertain to a memory system containing multiple memory devices, in which one or multiple ones of the memory devices may flexibly be selected at one time for a common operation to be performed by all the selected devices concurrently.

Abstract: A method, device, and system are disclosed. In one embodiment, the device comprises an array of flash memory blocks to store information in a multiple bit per cell mode, one or more flash memory blocks external to the array to store information in a single bit per cell mode, and a memory controller capable of allowing access to the array and the one or more flash memory blocks external to the array.