Abstract: A leadframe has conductive fingers with an insulating film located on a first portion of the fingers. The insulating film has openings into which contact pads formed of a noble metal are provided. Pads on a chip are wire bonded to these contact pads on the leadframe. The first portion is encapsulated in a molded package. The structure inhibits silver migration, provides insulation between wires and leadframe, and provides improved adhesion between plastic package and leadframe. A single insulating film with openings for providing the contact pads provides all these features.

Abstract: Silicon and germanium containing materials are used at surface of conductors in electronic devices. Solder can be fluxlessly bonded and wires can be wire bonded to these surfaces. These material are used as a surface coating for lead frames for packaging integrated circuit chips. These materials can be decal transferred onto conductor surfaces or electrolessly or electrolytically disposed thereon.

Abstract: A leadframe has conductive fingers with an insulating film located on a first portion of the fingers. The insulating film has openings into which contact pads formed of a noble metal are provided. Pads on a chip are wire bonded to these contact pads on the leadframe. The first portion is encapsulated in a molded package. The structure inhibits silver migration, provides insulation between wires and leadframe, and provides improved adhesion between plastic package and leadframe. A single insulating film with openings for providing the contact pads provides all these features.

Abstract: A lead on chip (LOC) semiconductor leadframe package provides notched lead-fingers to eliminate mechanical shear-stress at the peripheral edge of a semiconductor chip. Opposite rows of substantially flat cantilevered lead-fingers are attached by double-sided adhesive tape in thermal contact with the active face of a chip. The lead-fingers are routed in personalized paths over the face of the chip to cover a large surface area to aid heat dissipation. All wirebond connections between the lead-fingers and the chip are made at a centerline connection strip running down the center of the chip. Each of the cantilevered lead-fingers has a notched portion positioned directly over the vulnerable peripheral chip edge to reduce thermal, mechanical shear-stress. Additionally, since corrosion typically follows a lead path, the notch provides increasing path length to prevent corrosive ingress over the chip face.

Abstract: A lead on chip (LOC) semiconductor leadframe package provides notched lead-fingers to eliminate mechanical shear-stress at the peripheral edge of a semiconductor chip. Opposite rows of substantially flat cantilevered lead-fingers are attached by double-sided adhesive tape in thermal contact with the active face of a chip. The lead-fingers are routed in personalized paths over the face of the chip to cover a large surface area to aid heat dissipation. All wirebond connections between the lead-fingers and the chip are made at a centerline connection strip running down the center of the chip. Each of the cantilevered lead-fingers has a notched portion positioned directly over the vulnerable peripheral chip edge to reduce thermal, mechanical shear-stress. Additionally, since corrosion typically follows a lead path, the notch provides an increasing path length to prevent corrosive ingress over the chip face.