Patents by Inventor Sheldon Haynie

Sheldon Haynie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for integrating MIM capacitor and thin film resistor in modular two layer metal process and corresponding device
    Patent number: 8445353
    Abstract: A method for integrating a metal-insulator-metal (MIM) capacitor and a thin film resistor in an integrated circuit is provided that includes depositing a first metal layer outwardly of a semiconductor wafer substrate. A portion of the first metal layer forms a bottom plate for a MIM capacitor. A second metal layer is deposited outwardly of the first metal layer. A first portion of the second metal layer forms a top plate for the MIM capacitor and a second portion of the second metal layer forms contact pads for a thin film resistor.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: May 21, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Venkat Raghavan, Sheldon Haynie, Andrew Strachan
  • Transistors formed with grid or island implantation masks to form reduced diffusion-depth regions without additional masks and process steps
    Patent number: 6869851
    Abstract: A method of forming two regions having differing depths using a single implantation process is provided. A mask having two openings associated therewith is formed over a semiconductor body, wherein one of the openings has a size larger than an implantation design rule, and the other opening has a size smaller than the design rule. An implant is performed into the semiconductor body through the implant mask, resulting in two distinct doped regions, wherein the region associated with the larger opening has more dopant than the region associated with the smaller opening. Subsequent activation and thermal processing results in the one region diffusing a greater amount than the second region, thereby resulting in two regions formed concurrently having different depths.
    Type: Grant
    Filed: January 20, 2004
    Date of Patent: March 22, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Joe R. Trogolo, Lily Springer, Jeff Smith, Sheldon Haynie
  • Transistors formed with grid or island implantation masks to form reduced diffusion-depth regions without additional masks and process steps
    Patent number: 6716709
    Abstract: A method of forming two regions having differing depths using a single implantation process is provided. A mask having two openings associated therewith is formed over a semiconductor body, wherein one of the openings has a size larger than an implantation design rule, and the other opening has a size smaller than the design rule. An implant is performed into the semiconductor body through the implant mask, resulting in two distinct doped regions, wherein the region associated with the larger opening has more dopant than the region associated with the smaller opening. Subsequent activation and thermal processing results in the one region diffusing a greater amount than the second region, thereby resulting in two regions formed concurrently having different depths.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: April 6, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Lily Springer, Jeff Smith, Sheldon Haynie, Joe R. Trogolo