Abstract: A count value generator includes an input for receiving a synchronizing count value, a counter configured to increment at a local frequency, the local frequency being faster than the synchronizing frequency, and an interpolator for determining a frequency ratio between the local frequency and the synchronizing frequency and for determining an increment value for the counter dependent on a relative amount of a maximum value of the counter with respect to the frequency ratio is disclosed. The counter generates a count value including a predetermined number of bits representing integer values and output as the lower order bits of the output count value and additional lower order bits that represent fractional portions of the integer values. The counter includes output circuitry for outputting the synchronizing count value and the predetermined number of bits representing integer values generated by the counter as the lower order bits of the count value.

Abstract: A data processing apparatus is disclosed, said data processing apparatus comprising a plurality of devices, trace logic associated with at least one of said plurality of devices, and tagging logic associated with at least one of said plurality of devices, said tagging logic being operable to: select at least one item, said at least one item comprising an activity to be monitored; provide said at least one selected item with tag data identifying said at least one item as an item to be monitored; and said trace logic being operable to: detect tagged items processed by said at least one device; and output trace information relating to at least some of said detected tagged items.

Abstract: A data processing apparatus having one or more trace data sources. At least one of said trace data sources includes a trace data generator responsive to activity in monitored circuitry to generate trace data representing said activity. A synchronization marker generator is coupled to the trace data generator and operates to generate a synchronization marker and insert the synchronization marker into the trace data stream. A controller is coupled to the synchronization marker generator to generate and insert a synchronization marker into the trace data stream. The controller controls initiation in dependence on behavior of the data processing apparatus downstream of the trace data generator. In this way, the downstream behavior of the data processing apparatus can be made to influence the rate and timing of insertion of synchronization markers into a trace data stream.

Abstract: A count value generator includes an input for receiving a synchronising count value, a counter configured to increment at a local frequency, the local frequency being faster than the synchronising frequency, and an interpolator for determining a frequency ratio between the local frequency and the synchronising frequency and for determining an increment value for the counter dependent on a relative amount of a maximum value of the counter with respect to the frequency ratio is disclosed. The counter generates a count value including a predetermined number of bits representing integer values and output as the lower order bits of the output count value and additional lower order bits that represent fractional portions of the integer values. The counter includes output circuitry for outputting the synchronising count value and the predetermined number of bits representing integer values generated by the counter as the lower order bits of the count value.

Abstract: An integrated circuit 300 includes a functional circuit 310 and a diagnostic circuit 330. The integrated circuit includes a signal interface controller 320 operable to monitor a signal associated with at least one of the functional circuit and the diagnostic circuit to control selective communication of a diagnostic signal and a functional signal for communication across a signal interface in dependence upon the monitored signal. A further integrated circuit has a signal interface providing a communication path and communicates a functional signal having at least one multi-bit value in which at least one bit is replaced by data of a diagnostic signal.

Abstract: A data processing apparatus having one or more trace data sources. At least one of said trace data sources includes a trace data generator responsive to activity in monitored circuitry to generate trace data representing said activity. A synchronization marker generator is coupled to the trace data generator and operates to generate a synchronization marker and insert the synchronization marker into the trace data stream. A controller is coupled to the synchronization marker generator to generate and insert a synchronization marker into the trace data stream. The controller controls initiation in dependence on behavior of the data processing apparatus downstream of the trace data generator. In this way, the downstream behavior of the data processing apparatus can be made to influence the rate and timing of insertion of synchronization markers into a trace data stream.

Abstract: A data processing apparatus having one or more trace data sources. At least one of said trace data sources includes a trace data generator responsive to activity in monitored circuitry to generate trace data representing said activity. A synchronization marker generator is coupled to the trace data generator and operates to generate a synchronization marker and insert the synchronization marker into the trace data stream. A controller is coupled to the synchronization marker generator to generate and insert a synchronization marker into the trace data stream. The controller controls initiation in dependence on behavior of the data processing apparatus downstream of the trace data generator. In this way, the downstream behavior of the data processing apparatus can be made to influence the rate and timing of insertion of synchronization markers into a trace data stream.

Abstract: An integrated circuit 300 includes a functional circuit 310 and a diagnostic circuit 330. The integrated circuit includes a signal interface controller 320 operable to monitor a signal associated with at least one of the functional circuit and the diagnostic circuit to control selective communication of a diagnostic signal and a functional signal for communication across a signal interface in dependence upon the monitored signal. A further integrated circuit has a signal interface providing a communication path and communicates a functional signal having at least one multi-bit value in which at least one bit is replaced by data of a diagnostic signal.

Abstract: An integrated circuit 300 includes a functional circuit 310 and a diagnostic circuit 330. The integrated circuit includes a signal interface controller 320 operable to monitor a signal associated with at least one of the functional circuit and the diagnostic circuit to control selective communication of a diagnostic signal and a functional signal for communication across a signal interface in dependence upon the monitored signal. A further integrated circuit has a signal interface providing a communication path and communicates a functional signal having at least one multi-bit value in which at least one bit is replaced by data of a diagnostic signal.

Abstract: Within an integrated circuit (2) independently controllable domains (4, 6, 8, 10, 5 12, 14) may be unable to complete pending transactions taking place between domains. Each domain is provided with a state machine (20, 22) which is responsive to the state of the state machine within the other domain and when this indicates that the other domain is not communicating triggers modified behavior. This can provide that the predetermined transaction protocol is not broken and/or complete a partially completed transaction when the domain concerned has recovered from an error or other event which disrupted the communication.

Abstract: A data processing apparatus having one or more trace data sources is provided in which the trace data sources operate to generate respective streams of trace data. At least one of said trace data sources comprises a trace data generator responsive to activity in monitored circuitry to generate trace data representing said activity. A synchronization marker generator is coupled to the trace data generator and operates to generate a synchronization marker and insert the synchronization marker into the trace data stream. The synchronization marker identifies a synchronization position in the trace data stream. A controller is coupled to the synchronization marker generator, and operates to initiate the synchronization marker generator to generate and insert a synchronization marker into the trace data stream. The controller controls initiation in dependence on behavior of the data processing apparatus downstream of the trace data generator with respect to trace data flow.

Abstract: A data processing apparatus is disclosed, said data processing apparatus comprising a plurality of devices, trace logic associated with at least one of said plurality of devices, and tagging logic associated with at least one of said plurality of devices, said tagging logic being operable to: select at least one item, said at least one item comprising an activity to be monitored; provide said at least one selected item with tag data identifying said at least one item as an item to be monitored; and said trace logic being operable to: detect tagged items processed by said at least one device; and output trace information relating to at least some of said detected tagged items.

Abstract: A data processing apparatus and method for generating trace elements is provided. The data processing apparatus comprises logic producing a series of data elements, indicative of the operation or state of all or part of the logic. Trace logic is provided for receiving indications of these data elements, and for generating from the indications a stream of trace elements. When for a given data element, at least part of the data element is derivable from a reference to a control value stored in a storage element, the trace logic is operable, dependent on that data element, to omit that part of the associated data element indication from the corresponding trace element generated in respect of the data element, instead including a reference to the corresponding storage element. A trace analysing apparatus can then be used to reconstruct such omitted information based on a copy of the relevant storage element.

Abstract: An integrated circuit 300 includes a functional circuit 320 and a diagnostic circuit 330. The integrated circuit comprises a signal interface controller 320 operable to monitor a signal associated with at least one of the functional circuit and the diagnostic circuit to control selective communication of a diagnostic signal and a functional signal for communication across a signal interface in dependence upon the monitored signal. A further integrated circuit has a signal interface providing a communication path and communicates a functional signal having at least one multi-bit value in which at least one bit is replaced by data of a diagnostic signal.

Abstract: A trace data formatter 30 assembles trace data frames 50. These trace data frames 50 include bytes which may either serve to carry a trace data source identifier ID or trace data. A system being traced has multiple trace data sources 12, 14, 16, 18 and when the trace data source which is generating the current trace data stream changes then a trace data source identifier ID is inserted within the trace data stream.

Abstract: A trace data system is provided in which flush request signals are generated and passed to trace data sources to trigger them to output any buffered trace data they are storing which was generated prior to the flush request being signalled. When the trace data has been flushed from these trace data sources, they signal this by generating a flush complete signal. The flushing of trace data may advantageously be performed prior to a power-down operation and using a trace bus bridge.

Abstract: Within an integrated circuit 2 independently controllable domains 4, 6, 8, 10, 12, 14 may be unable to complete pending transactions taking place between domains. Each domain is provided with a transaction level state machine 20, 22 which is responsive to the state of the state machine within the other domain and when this indicates that the other domain is not capable of communicating triggers default behavior ensuring that the predetermined transaction protocol is not broken.

Abstract: An integrated circuit 2 is provided with multiple sources 12, 14, 16, 18 of trace data streams that are input via respective dedicated trace buses 20, 24 to a trace data stream combiner 22, 26. The trace data bus has trace data signal lines ATDATA for carrying trace data signals and trace source identifying signal lines ATID for carrying trace source identifying signals. A trace data stream replicator 28 may be used to replicate a single trace data stream such that the resulting multiple trace data streams may be subject to different post-replication processing/filtering as desired.

Abstract: An integrated circuit is provided with multiple data processing components associated with respective sources which generate trace data streams. A reference timestamp generator is provided and the trace data streams are annotated such that they are output off-chip together with reference timestamp data. Outputting the reference timestamp data together with the trace data streams enables temporal correlation between points in different trace data streams by trace analysis tools.