Abstract: A digital control scheme controls an integrator of a PID filter to implement non-linear control of saturating the duty cycle during which the proportional and derivative terms of the PID filter are set to 0 while the integrator and its internal states (previous values or memory) is set to a duty cycle that is the sum of the current nominal duty cycle plus a deltaD. The deltaD is the maximum duty cycle increment that is used to regulate a voltage regulator from ICCmin to ICCmax and is a configuration register that can be set post silicon. An FSM moves from a non-linear all ON state to an open loop duty cycle which maintains the output voltage slightly higher than the required Vref. After a certain period in this open loop, the FSM then ramps down the open loop duty cycle value until the output voltage is close to the Vref.

Abstract: A digital control scheme controls an integrator of a PID filter to implement non-linear control of saturating the duty cycle during which the proportional and derivative terms of the PID filter are set to 0 while the integrator and its internal states (previous values or memory) is set to a duty cycle that is the sum of the current nominal duty cycle plus a deltaD. The deltaD is the maximum duty cycle increment that is used to regulate a voltage regulator from ICCmin to ICCmax and is a configuration register that can be set post silicon. An FSM moves from a non-linear all ON state to an open loop duty cycle which maintains the output voltage slightly higher than the required Vref. After a certain period in this open loop, the FSM then ramps down the open loop duty cycle value until the output voltage is close to the Vref.

Abstract: Methods and apparatus relating to low cost and/or low overhead serial interface for power management and other IC (Integrated Circuit) devices are described. In an embodiment, a unique address is assigned to each of a plurality of slave devices. The plurality of slave devices are coupled in a daisy chain configuration. And, any access directed at a first slave device from the plurality of slave devices is allowed based at least in part on comparison of an address of the first slave device and an address associated with the access. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus relating to reducing switching noise and improving transient response in voltage regulators are described. In an embodiment, one or more pulses are inserted into an output waveform of a voltage regulator. The one or more pulses introduce multiple frequencies into the output waveform of the voltage regulator (e.g., to reduce acoustic noise). In another embodiment, the output voltage of a voltage regulator is modified in response to comparison of the output voltage with at least one of a plurality of threshold values. The plurality of threshold values includes an upper trigger point voltage value and a lower trigger point voltage value. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus relating to low cost and/or low overhead serial interface for power management and other IC (Integrated Circuit) devices are described. In an embodiment, a unique address is assigned to each of a plurality of slave devices. The plurality of slave devices are coupled in a daisy chain configuration. And, any access directed at a first slave device from the plurality of slave devices is allowed based at least in part on comparison of an address of the first slave device and an address associated with the access. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus relating to reducing switching noise and improving transient response in voltage regulators are described. In an embodiment, one or more pulses are inserted into an output waveform of a voltage regulator. The one or more pulses introduce multiple frequencies into the output waveform of the voltage regulator (e.g., to reduce acoustic noise). In another embodiment, the output voltage of a voltage regulator is modified in response to comparison of the output voltage with at least one of a plurality of threshold values. The plurality of threshold values includes an upper trigger point voltage value and a lower trigger point voltage value. Other embodiments are also disclosed and claimed.