Abstract: A method of generating simulated data signals, data processing system and software model are disclosed. The method comprises the steps of: a) providing input data signals to a component of a data processing apparatus; b) capturing a representation of the input data signals; c) providing a software model operable to simulate the behaviour of the component of the data processing apparatus; and d) executing the software model using the captured representation of the input data signals to generate simulated data signals representing the behaviour of the component of the data processing apparatus in response to the input data signals. Using a software model to emulate the behaviour of the component in response to the input data signals obviates the need to manufacture a test chip for debugging purposes. Also, any timing issues which arise when using a test chip can be obviated by using a software model.

Abstract: A data processing apparatus and method for generating trace elements is provided. The data processing apparatus comprises logic producing a series of data elements, indicative of the operation or state of all or part of the logic. Trace logic is provided for receiving indications of these data elements, and for generating from the indications a stream of trace elements. When for a given data element, at least part of the data element is derivable from a reference to a control value stored in a storage element, the trace logic is operable, dependent on that data element, to omit that part of the associated data element indication from the corresponding trace element generated in respect of the data element, instead including a reference to the corresponding storage element. A trace analysing apparatus can then be used to reconstruct such omitted information based on a copy of the relevant storage element.

Abstract: Within an integrated circuit 2 independently controllable domains 4, 6, 8, 10, 12, 14 may be unable to complete pending transactions taking place between domains. Each domain is provided with a state machine 20, 22 which is responsive to the state of the state machine within the other domain and when this indicates that the other domain is not communicating triggers modified behaviour. This can provide that the predetermined transaction protocol is not broken and/or complete a partially completed transaction when the domain concerned has recovered from an error or other event which disrupted the communication.

Abstract: Within an integrated circuit 2 independently controllable domains 4, 6, 8, 10, 12, 14 may be unable to complete pending transactions taking place between domains. Each domain is provided with a transaction level state machine 20, 22 which is responsive to the state of the state machine within the other domain and when this indicates that the other domain is not capable of communicating triggers default behaviour ensuring that the predetermined transaction protocol is not broken.

Abstract: A trace data system is provided in which flush request signals are generated and passed to trace data sources to trigger them to output any buffered trace data they are storing which was generated prior to the flush request being signalled. When the trace data has been flushed from these trace data sources, they signal this by generating a flush complete signal. The flushing of trace data may advantageously be performed prior to a power-down operation and using a trace bus bridge.

Abstract: A trace data formatter 30 assembles trace data frames 50. These trace data frames 50 include bytes which may either serve to carry a trace data source identifier ID or trace data. A system being traced has multiple trace data sources 12, 14, 16, 18 and when the trace data source which is generating the current trace data stream changes then a trace data source identifier ID is inserted within the trace data stream.

Abstract: An integrated circuit 2 is provided with multiple sources 12, 14, 16, 18 of trace data streams that are input via respective dedicated trace buses 20, 24 to a trace data stream combiner 22, 26. The trace data bus has trace data signal lines ATDATA for carrying trace data signals and trace source identifying signal lines ATID for carrying trace source identifying signals. A trace data stream replicator 28 may be used to replicate a single trace data stream such that the resulting multiple trace data streams may be subject to different post-replication processing/filtering as desired.

Abstract: An integrated circuit is provided with multiple data processing components associated with respective sources which generate trace data streams. A reference timestamp generator is provided and the trace data streams are annotated such that they are output off-chip together with reference timestamp data. Outputting the reference timestamp data together with the trace data streams enables temporal correlation between points in different trace data streams by trace analysis tools.