Abstract: A fixing fixture adapted to fix an assembling component is provided. The fixing fixture includes a base and at least one positioning component. The positioning component is pivoted with the base and has a supporting portion and a positioning portion. When the positioning component is located at a first position, the assembling component is adapted to push the supporting portion to drive the positioning component to rotate to a second position, such that the positioning portion is closely pressed against the assembling component. When the positioning component is located at the second position and the positioning portion is closely pressed against the assembling component, a fastening component is adapted to rotate along an axis to be fastened onto the assembling component, and the positioning portion stops the assembling component from rotating along the axis with the fastening component.

Abstract: A fixing fixture adapted to fix an assembling component is provided. The fixing fixture includes a base and at least one positioning component. The positioning component is pivoted with the base and has a supporting portion and a positioning portion. When the positioning component is located at a first position, the assembling component is adapted to push the supporting portion to drive the positioning component to rotate to a second position, such that the positioning portion is closely pressed against the assembling component. When the positioning component is located at the second position and the positioning portion is closely pressed against the assembling component, a fastening component is adapted to rotate along an axis to be fastened onto the assembling component, and the positioning portion stops the assembling component from rotating along the axis with the fastening component.

Abstract: In some embodiments, a chip includes a link interface, monitoring circuitry to provide an activity indicator that is indicative of activity of the chip, and scheduling circuitry to schedule commands. The chip also includes mode selection circuitry to select a first mode or a second mode for the scheduling circuitry depending on the activity indicator, wherein in the first mode the scheduling circuitry schedules certain commands as separate single commands and in the second mode the scheduling circuitry schedules at least one consolidated command to represent more than one of the separate single commands. Other embodiments are described.

Abstract: In some embodiments, a chip includes a request queue to include write requests, and scheduling circuitry to schedule commands including commands in response to the write requests. The chip also includes mode selection circuitry to monitor the request queue and in response thereto to select a first or a second mode for the scheduling circuitry, wherein in the first mode the scheduling circuitry schedules certain commands as separate single commands and in the second mode the scheduling circuitry schedules consolidated commands to represent more than one separate single command. Other embodiments are described.

Abstract: In some embodiments, a chip includes a link interface, monitoring circuitry to provide an activity indicator that is indicative of activity of the chip, and scheduling circuitry to schedule commands. The chip also includes mode selection circuitry to select a first mode or a second mode for the scheduling circuitry depending on the activity indicator, wherein in the first mode the scheduling circuitry schedules certain commands as separate single commands and in the second mode the scheduling circuitry schedules at least one consolidated command to represent more than one of the separate single commands. Other embodiments are described.

Abstract: In some embodiments, a chip includes a request queue to include write requests, and scheduling circuitry to schedule commands including commands in response to the write requests. The chip also includes mode selection circuitry to monitor the request queue and in response thereto to select a first or a second mode for the scheduling circuitry, wherein in the first mode the scheduling circuitry schedules certain commands as separate single commands and in the second mode the scheduling circuitry schedules consolidated commands to represent more than one separate single command. Other embodiments are described.