Abstract: A chip package array including a plurality of chip packages is provided. The chip packages are suitable for array arrangement to form the chip package array. Each of the chip packages includes a redistribution structure, a supporting structure, a chip, and an encapsulated material. The supporting structure is disposed on the redistribution structure and has an opening. The chip is disposed on the redistribution structure and located in the opening. The encapsulated material is located between the opening and the chip, wherein the encapsulated material is filled between the opening and the chip, and the chip and the supporting structure are respectively connected to the redistribution structure.

Abstract: A chip package process includes the following steps. A supporting structure and a carrier plate are provided. The supporting structure has a plurality of openings. The supporting structure is disposed on the carrier plate. A plurality of chips is disposed on the carrier plate. The chips are respectively located in the openings of the supporting structure. An encapsulated material is formed to cover the supporting structure and the chips. The supporting structure and the chips are located between the encapsulated material and the carrier plate. The encapsulated material is filled between the openings and the chips. The carrier plate is removed. A redistribution structure is disposed on the supporting structure, wherein the redistribution structure is connected to the chips.

Abstract: A chip packaging method includes followings steps. A plurality of first chips are disposed on a carrier, wherein each of the first chips has a first active surface, and a plurality of first conductive pillars are disposed on the first active surface. A second active surface of a second chip is electrically connected to the first active surfaces of the first chips through a plurality of second conductive pillars. An encapsulated material is formed, wherein the encapsulated material covers the plurality of first chips, the plurality of first conductive pillars, the second chip and the plurality of second conductive pillars. The encapsulated material is partially removed to expose each of the plurality of first conductive pillars. A redistribution structure is formed on the encapsulated material, wherein the redistribution structure connects with the first conductive pillars.

Abstract: A chip package structure includes a plurality of first chips, a plurality of first conductive pillars, a second chip, a plurality of second conductive pillars, an encapsulated material and a redistribution structure. Each first chip has a first active surface. Each of the first conductive pillars is disposed on the first active surface of the corresponding first chip. A second active surface of the second chip is electrically connected to the first active surfaces of the first chips through the second conductive pillars. The encapsulated material partially covers the first chips, the first conductive pillars, the second chip and the second conductive pillars. The redistribution structure is disposed on the encapsulated material and connects the first conductive pillars. A chip package structure array is also provided.

Abstract: A chip packaging method includes followings steps. A plurality of first chips are disposed on a carrier, wherein each of the first chips has a first active surface, and a plurality of first conductive pillars are disposed on the first active surface. A second active surface of a second chip is electrically connected to the first active surfaces of the first chips through a plurality of second conductive pillars. An encapsulated material is formed, wherein the encapsulated material covers the plurality of first chips, the plurality of first conductive pillars, the second chip and the plurality of second conductive pillars. The encapsulated material is partially removed to expose each of the plurality of first conductive pillars. A redistribution structure is formed on the encapsulated material, wherein the redistribution structure connects with the first conductive pillars.

Abstract: A chip package structure includes a plurality of first chips, a plurality of first conductive pillars, a second chip, a plurality of second conductive pillars, an encapsulated material and a redistribution structure. Each first chip has a first active surface. Each of the first conductive pillars is disposed on the first active surface of the corresponding first chip. A second active surface of the second chip is electrically connected to the first active surfaces of the first chips through the second conductive pillars. The encapsulated material partially covers the first chips, the first conductive pillars, the second chip and the second conductive pillars. The redistribution structure is disposed on the encapsulated material and connects the first conductive pillars. A chip package structure array is also provided.

Abstract: A chip package process includes the following steps. A supporting structure and a carrier plate are provided. The supporting structure has a plurality of openings. The supporting structure is disposed on the carrier plate. A plurality of chips is disposed on the carrier plate. The chips are respectively located in the openings of the supporting structure. An encapsulated material is formed to cover the supporting structure and the chips. The supporting structure and the chips are located between the encapsulated material and the carrier plate. The encapsulated material is filled between the openings and the chips. The carrier plate is removed. A redistribution structure is disposed on the supporting structure, wherein the redistribution structure is connected to the chips.

Abstract: A chip package array including a plurality of chip packages is provided. The chip packages are suitable for array arrangement to form the chip package array. Each of the chip packages includes a redistribution structure, a supporting structure, a chip, and an encapsulated material. The supporting structure is disposed on the redistribution structure and has an opening. The chip is disposed on the redistribution structure and located in the opening. The encapsulated material is located between the opening and the chip, wherein the encapsulated material is filled between the opening and the chip, and the chip and the supporting structure are respectively connected to the redistribution structure.

Abstract: The present invention provides a chip and its manufacturing methods and applications. Regarding the chip, there are several solder bumps on the backside of the chip. The difference of the invented chip from the convention chips is that the solder bumps are embedded in an insulting layer and a thermal-plastic material layer of the invented chip backside and separated by a conductive layer from the insulting layer and thermal-plastic material layer. Additionally, there are some end members in the insulting layer, and the end member corresponds to one solder bump. Through the present invention, chips with different functions can be integrated together, so that the needs for having portable communication devices lighter and smaller would be met.

Abstract: The present invention provides a chip and its manufacturing methods and applications. Regarding the chip, there are several solder bumps on the backside of the chip. The difference of the invented chip from the convention chips is that the solder bumps are embedded in an insulting layer and a thermal-plastic material layer of the invented chip backside and separated by a conductive layer from the insulting layer and thermal-plastic material layer. Additionally, there are some end members in the insulting layer, and the end member corresponds to one solder bump. Through the present invention, chips with different functions can be integrated together, so that the needs for having portable communication devices lighter and smaller would be met.

Abstract: A flip chip test structure is disclosed. The flip chip test structure utilizes a substrate used in flip chip package to replace the conventional transformer of a flip chip wafer probe card. The substrate-transformer replacement reduces the cost and simplifies the flip chip wafer probe card manufacturing process since the substrate is already available and matches the chip being tested while the transformer needs additional design and custom fabrication which are expensive and time-wasting for corresponding chip being tested.

Abstract: A hybrid integrated circuit (IC) package substrate at least comprising a plurality of patterned conductive layers stacked over each other. The outermost patterned conductive layer has a plurality of bonding pads thereon. The hybrid IC package substrate also has a plurality of dielectric layers respectively sandwiched between two neighboring patterned conductive layers. At least one of the dielectric layers is a ceramic dielectric layer and at least one of the remaining dielectric layers is an organic dielectric layer. There is also a plurality of vias passing through at least one of the dielectric layers for connecting at least two patterned conductive layers electrically.

Abstract: A hybrid integrated circuit (IC) package substrate at least comprising a plurality of patterned conductive layers stacked over each other. The outermost patterned conductive layer has a plurality of bonding pads thereon. The hybrid IC package substrate also has a plurality of dielectric layers respectively sandwiched between two neighboring patterned conductive layers. At least one of the dielectric layers is a ceramic dielectric layer and at least one of the remaining dielectric layers is an organic dielectric layer. There is also a plurality of vias passing through at least one of the dielectric layers for connecting at least two patterned conductive layers electrically.

Abstract: A system for coordinated inter-organizational information sharing. The system includes an information exchange center, a design organization, a production organization, a test organization, and an application design organization. The production organization manufactures the product according to the design specification designed by the design organization, and sends manufacturing problems to the information exchange center. The test organization tests the product, and sends test problems to the information exchange center. The application design organization designs peripheral applications according to the design specification without the product, tests the peripheral applications with the product, and sends application test problems to the information exchange center.

Abstract: A flip chip test structure is disclosed. The flip chip test structure utilizes a substrate used in flip chip package to replace the conventional transformer of a flip chip wafer probe card. The substrate-transformer replacement reduces the cost and simplifies the flip chip wafer probe card manufacturing process since the substrate is already available and matches the chip being tested while the transformer needs additional design and custom fabrication which are expensive and time-wasting for corresponding chip being tested.

Abstract: A bump arrangement of a flip-chip is disclosed. The bump arrangement comprises: a conductive bumps array formed at a core region of the flip-chip, a first ring of conductive bumps surrounding the conductive bumps array, a second ring surrounding the first ring, a third ring surrounding the second ring, and a fourth ring surrounding the third ring. In the four rings of bumps, the bumps of the third ring and the fourth ring are staggered each other and most of them are provided for I/O signal terminal so as to reduce the length conductive traces for I/O signal connection. The bumps in the first and the second ring are provided for power connection or ground connection. The first ring, the second ring, the third ring, the fourth ring and the bump at the core region are connected to conductive traces of an interconnection layer through a redistribution layer. The redistribution layer is located in between a passivation layer and the interconnection layer.

Abstract: A system for coordinated inter-organizational information sharing. The system includes an information exchange center, a design organization, a production organization, a test organization, and an application design organization. The production organization manufactures the product according to the design specification designed by the design organization, and sends manufacturing problems to the information exchange center. The test organization tests the product, and sends test problems to the information exchange center. The application design organization designs peripheral applications according to the design specification without the product, tests the peripheral applications with the product, and sends application test problems to the information exchange center.

Abstract: A bump arrangement of a flip-chip is disclosed. The bump arrangement comprises: a conductive bumps array formed at a core region of the flip-chip, a first ring of conductive bumps surrounding the conductive bumps array, a second ring surrounding the first ring, a third ring surrounding the second ring, and a fourth ring surrounding the third ring. In the four rings of bumps, the bumps of the third ring and the fourth ring are staggered each other and most of them are provided for I/O signal terminal so as to reduce the length conductive traces for I/O signal connection. The bumps in the first and the second ring are provided for power connection or ground connection. The first ring, the second ring, the third ring, the fourth ring and the bump at the core region are connected to conductive traces of an interconnection layer through a redistribution layer. The redistribution layer is located in between a passivation layer and the interconnection layer.

Abstract: Systems and methods are described for network address lookup entry aging in a DRAM memory. A method of DRAM data aging includes: refreshing a row of memory cells in an array of DRAM memory cells. The refreshing periodically includes aging all entries that are stored in the row of memory cells. The systems and methods provide advantages in that an existing operation is used for an additional function. In addition, the aging can be implemented with closely coupled logic using the sense amplifiers.

Abstract: Systems and methods are described for distributed DRAM refreshing. A method of distributed DRAM refreshing includes: refreshing a first row of memory cells in a first array of DRAM memory cells with a first row of sense amplifiers; and then refreshing a second row of memory cells in a second array of DRAM memory cells with a second row of sense amplifiers. The systems and methods provide advantages in that magnitude of power transients (noise) can be reduced. In addition, the performance can be improved when the arrays are arranged in multiple sub-groups.