Patents by Inventor Shen-De Wang

Shen-De Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12010931
    Abstract: A RRAM (resistive random-access memory) device includes a bottom electrode line, a top electrode island and a resistive material. The bottom electrode line is directly on a first metal structure. The top electrode island is disposed beside the bottom electrode line. The resistive material is sandwiched by a sidewall of the bottom electrode line and a sidewall of the top electrode island. The present invention also provides a method of forming said RRAM device.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: June 11, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Ching Hsu, Wang Xiang, Shen-De Wang
  • Patent number: 11990546
    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, a first oxide layer, a field plate, and a second oxide layer. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure respectively. The first oxide layer includes a first portion disposed between the gate structure and the semiconductor substrate and a second portion disposed between the gate structure and the drain region. The field plate is partly disposed above the gate structure and partly disposed above the second portion of the first oxide layer. The second oxide layer includes a first portion disposed between the field plate and the gate structure and a second portion disposed between the field plate and the second portion of the first oxide layer.
    Type: Grant
    Filed: March 13, 2023
    Date of Patent: May 21, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Cheng-Hua Yang, Chih-Chien Chang, Shen-De Wang
  • Publication number: 20240155843
    Abstract: A semiconductor device includes a substrate having a flash memory region and a logic device region, a logic transistor disposed in the logic device region, and a flash memory transistor disposed in the flash memory region. The flash memory transistor includes a metal select gate having two opposite sidewalls and two memory gates disposed on the two opposite sidewalls of the metal select gate.
    Type: Application
    Filed: November 28, 2022
    Publication date: May 9, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Wang Xiang, CHIA CHING HSU, Shen-De Wang, Yung-Lin Tseng, WEICHANG LIU
  • Publication number: 20240081158
    Abstract: An RRAM structure includes a dielectric layer. A bottom electrode, a resistive switching layer and a top electrode are disposed from bottom to top on the dielectric layer. A spacer is disposed at sidewalls of the bottom electrode, the resistive switching layer and the top electrode. The spacer includes an L-shaped spacer and a sail-shaped spacer. The L-shaped spacer contacts the sidewall of the bottom electrode, the sidewall of the resistive switching layer and the sidewall of the top electrode. The sail-shaped spacer is disposed on the L-shaped spacer. A metal line is disposed on the top electrode and contacts the top electrode and the spacer.
    Type: Application
    Filed: September 21, 2022
    Publication date: March 7, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Wei Cheng, ZHEN CHEN, Shen-De Wang
  • Publication number: 20240057488
    Abstract: A RRAM (resistive random-access memory) device includes a bottom electrode line, a top electrode island and a resistive material. The bottom electrode line is directly on a first metal structure. The top electrode island is disposed beside the bottom electrode line. The resistive material is sandwiched by a sidewall of the bottom electrode line and a sidewall of the top electrode island. The present invention also provides a method of forming the RRAM device.
    Type: Application
    Filed: October 19, 2023
    Publication date: February 15, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Ching Hsu, Wang Xiang, Shen-De Wang
  • Publication number: 20230268437
    Abstract: A power device includes a substrate, an ion well in the substrate, a body region in the ion well, a source doped region in the body region, a drain doped region in the ion well, and gates on the substrate between the source doped region and the drain doped region. The gates include a first gate adjacent to the source doped region, a second gate adjacent to the drain doped region, and a stacked gate structure between the first gate and the second gate.
    Type: Application
    Filed: March 24, 2022
    Publication date: August 24, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Chien Chang, Shen-De Wang, Cheng-Hua Yang, LINGGANG FANG, JIANJUN YANG, Wei Ta
  • Publication number: 20230215946
    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, a first oxide layer, a field plate, and a second oxide layer. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure respectively. The first oxide layer includes a first portion disposed between the gate structure and the semiconductor substrate and a second portion disposed between the gate structure and the drain region. The field plate is partly disposed above the gate structure and partly disposed above the second portion of the first oxide layer. The second oxide layer includes a first portion disposed between the field plate and the gate structure and a second portion disposed between the field plate and the second portion of the first oxide layer.
    Type: Application
    Filed: March 13, 2023
    Publication date: July 6, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Cheng-Hua Yang, Chih-Chien Chang, Shen-De Wang
  • Patent number: 11631766
    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, a first oxide layer, a field plate, and a second oxide layer. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure respectively. The first oxide layer includes a first portion disposed between the gate structure and the semiconductor substrate and a second portion disposed between the gate structure and the drain region. The field plate is partly disposed above the gate structure and partly disposed above the second portion of the first oxide layer. The second oxide layer includes a first portion disposed between the field plate and the gate structure and a second portion disposed between the field plate and the second portion of the first oxide layer.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: April 18, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Cheng-Hua Yang, Chih-Chien Chang, Shen-De Wang
  • Publication number: 20230099289
    Abstract: A semiconductor memory structure includes a substrate having a device cell region and a contact forming region in proximity to the device cell region. A memory cell transistor is disposed within the device cell region. The memory cell transistor includes a gate and a charge storage structure between the gate and the substrate. The gate includes an extended portion within the contact forming region. A first spacer is disposed on a sidewall of the gate within the device cell region. A second spacer is disposed on a sidewall of the extended portion of the gate within the contact forming region. The second spacer is higher than the first spacer.
    Type: Application
    Filed: October 14, 2021
    Publication date: March 30, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: ZHEN CHEN, Wei Cheng, KOK WUN TAN, Shen-De Wang
  • Publication number: 20220310839
    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, a first oxide layer, a field plate, and a second oxide layer. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure respectively. The first oxide layer includes a first portion disposed between the gate structure and the semiconductor substrate and a second portion disposed between the gate structure and the drain region. The field plate is partly disposed above the gate structure and partly disposed above the second portion of the first oxide layer. The second oxide layer includes a first portion disposed between the field plate and the gate structure and a second portion disposed between the field plate and the second portion of the first oxide layer.
    Type: Application
    Filed: April 12, 2021
    Publication date: September 29, 2022
    Inventors: Cheng-Hua Yang, Chih-Chien Chang, Shen-De Wang
  • Patent number: 11444095
    Abstract: A semiconductor device with integrated memory devices and metal-oxide-semiconductor (MOS) devices, including a substrate with a first area and a second area, multiple double-diffused metal-oxide-semiconductor (DMOS) devices on the first area, wherein the double-diffused metal-oxide-semiconductor (DMOS) device includes a field oxide on the substrate, a first gate dielectric layer adjacent to the field oxide, and a first polysilicon gate on the field oxide and the first gate dielectric layer, and multiple memory units on the second area, wherein the memory unit includes an oxide-nitride-oxide (ONO) tri-layer and a second polysilicon gate on the oxide-nitride-oxide (ONO) tri-layer, wherein a top surface of the second polysilicon gate of the memory unit in the second area and a top surface of the first polysilicon gate of the double-diffused metal-oxide-semiconductor (DMOS) in the first area are on the same level.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: September 13, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wang Xiang, Chia-Ching Hsu, Shen-De Wang, Weichang Liu
  • Publication number: 20220246845
    Abstract: A RRAM (resistive random-access memory) device includes a bottom electrode line, a top electrode island and a resistive material. The bottom electrode line is directly on a first metal structure. The top electrode island is disposed beside the bottom electrode line. The resistive material is sandwiched by a sidewall of the bottom electrode line and a sidewall of the top electrode island. The present invention also provides a method of forming said RRAM device.
    Type: Application
    Filed: March 9, 2021
    Publication date: August 4, 2022
    Inventors: Chia-Ching Hsu, Wang Xiang, Shen-De Wang
  • Patent number: 11387337
    Abstract: A memory device includes a main cell on a substrate, a first reference cell adjacent to one side of the main cell, and a second reference cell adjacent to another side of the main cell. Preferably, the main cell includes a first gate electrode on the substrate, a second gate electrode on one side of the first gate electrode and covering a top surface of the first gate electrode, a first charge trapping layer between the first gate electrode and the second gate electrode and including a first oxide-nitride-oxide (ONO) layer, a third gate electrode on another side of the first gate electrode and covering the top surface of the first gate electrode, and a second charge trapping layer between the first gate electrode and the third gate electrode and including a second ONO layer.
    Type: Grant
    Filed: December 24, 2020
    Date of Patent: July 12, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Sung Huang, Shen-De Wang, Chia-Ching Hsu, Wang Xiang
  • Patent number: 11127752
    Abstract: A semiconductor device includes a substrate, having cell region and high-voltage region. A memory cell is on the substrate within the cell region. The memory cell includes a memory gate structure and a selection gate structure on the substrate. A first spacer is sandwiched between or respectively on sidewalls of the memory cell structure and the selection gate structure. First high-voltage transistor is on the substrate within the high-voltage region. A first composite gate structure of the first high-voltage transistor includes a first gate structure on the substrate, an insulating layer with a predetermined thickness on the substrate in a -like structure or an L-like structure at cross-section, and a second gate structure on the insulating layer along the -like structure or the L-like structure. The selection gate structure and the second gate structure are originated from a same preliminary conductive layer.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: September 21, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Ching Hsu, Wang Xiang, Shen-De Wang, Chun-Sung Huang
  • Publication number: 20210265376
    Abstract: A semiconductor device includes a substrate, having cell region and high-voltage region. A memory cell is on the substrate within the cell region. The memory cell includes a memory gate structure and a selection gate structure on the substrate. A first spacer is sandwiched between or respectively on sidewalls of the memory cell structure and the selection gate structure. First high-voltage transistor is on the substrate within the high-voltage region. A first composite gate structure of the first high-voltage transistor includes a first gate structure on the substrate, an insulating layer with a predetermined thickness on the substrate in a -like structure or an L-like structure at cross-section, and a second gate structure on the insulating layer along the -like structure or the L-like structure. The selection gate structure and the second gate structure are originated from a same preliminary conductive layer.
    Type: Application
    Filed: February 21, 2020
    Publication date: August 26, 2021
    Applicant: United Microelectronics Corp.
    Inventors: CHIA-CHING HSU, Wang Xiang, Shen-De Wang, Chun-Sung Huang
  • Publication number: 20210233924
    Abstract: A semiconductor device with integrated memory devices and metal-oxide-semiconductor (MOS) devices, including a substrate with a first area and a second area, multiple double-diffused metal-oxide-semiconductor (DMOS) devices on the first area, wherein the double-diffused metal-oxide-semiconductor (DMOS) device includes a field oxide on the substrate, a first gate dielectric layer adjacent to the field oxide, and a first polysilicon gate on the field oxide and the first gate dielectric layer, and multiple memory units on the second area, wherein the memory unit includes an oxide-nitride-oxide (ONO) tri-layer and a second polysilicon gate on the oxide-nitride-oxide (ONO) tri-layer, wherein a top surface of the second polysilicon gate of the memory unit in the second area and a top surface of the first polysilicon gate of the double-diffused metal-oxide-semiconductor (DMOS) in the first area are on the same level.
    Type: Application
    Filed: April 13, 2021
    Publication date: July 29, 2021
    Inventors: Wang Xiang, Chia-Ching Hsu, Shen-De Wang, Weichang Liu
  • Patent number: 11011535
    Abstract: A method of integrating memory and metal-oxide-semiconductor (MOS) processes is provided, including steps of forming an oxide layer and a nitride layer on a substrate, forming a field oxide in a first area by an oxidation process with the nitride layer as a mask, wherein the oxidation process simultaneously forms a top oxide layer on the nitride layer, removing the top oxide layer, the nitride layer and the oxide layer in the first area, forming a polysilicon layer on the substrate, and patterning the polysilicon layer into MOS units in the first area and memory units in a second area.
    Type: Grant
    Filed: December 22, 2019
    Date of Patent: May 18, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wang Xiang, Chia-Ching Hsu, Shen-De Wang, Weichang Liu
  • Publication number: 20210119004
    Abstract: A memory device includes a main cell on a substrate, a first reference cell adjacent to one side of the main cell, and a second reference cell adjacent to another side of the main cell. Preferably, the main cell includes a first gate electrode on the substrate, a second gate electrode on one side of the first gate electrode and covering a top surface of the first gate electrode, a first charge trapping layer between the first gate electrode and the second gate electrode and including a first oxide-nitride-oxide (ONO) layer, a third gate electrode on another side of the first gate electrode and covering the top surface of the first gate electrode, and a second charge trapping layer between the first gate electrode and the third gate electrode and including a second ONO layer.
    Type: Application
    Filed: December 24, 2020
    Publication date: April 22, 2021
    Inventors: Chun-Sung Huang, Shen-De Wang, Chia-Ching Hsu, Wang Xiang
  • Patent number: 10903326
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first gate structure on a substrate; forming a second gate structure on the substrate and on one side of the first gate structure; forming a third gate structure on the substrate and on another side of the first gate structure; forming source/drain regions adjacent to the second gate structure and the third gate structure; and forming contact plugs to contact the first gate structure, the second gate structure, the third gate structure, and the source/drain regions.
    Type: Grant
    Filed: January 13, 2019
    Date of Patent: January 26, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Sung Huang, Shen-De Wang, Chia-Ching Hsu, Wang Xiang
  • Publication number: 20200227531
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first gate structure on a substrate; forming a second gate structure on the substrate and on one side of the first gate structure; forming a third gate structure on the substrate and on another side of the first gate structure; forming source/drain regions adjacent to the second gate structure and the third gate structure; and forming contact plugs to contact the first gate structure, the second gate structure, the third gate structure, and the source/drain regions.
    Type: Application
    Filed: January 13, 2019
    Publication date: July 16, 2020
    Inventors: Chun-Sung Huang, Shen-De Wang, Chia-Ching Hsu, Wang Xiang