Abstract: The present disclosure provides a memory control circuit configured to precede a data-reading process with a memory. For the data-reading process, the memory transmits a DQ and a DQS indicating a time to read the DQ. The DQS includes a preamble. The memory control circuit includes a control circuit and a sampling circuit. The control circuit is configured to generate an enabling signal. The sampling circuit coupled to the control circuit is configured to sample the DQS based on the enabling signal in order to determine a sampling level. The control circuit determines whether the sampling level matches a signal level of the preamble or not.

Abstract: The present disclosure provides a memory control circuit configured to precede a data-reading process with a memory. For the data-reading process, the memory transmits a DQ and a DQS indicating a time to read the DQ. The DQS includes a preamble. The memory control circuit includes a control circuit and a sampling circuit. The control circuit is configured to generate an enabling signal. The sampling circuit coupled to the control circuit is configured to sample the DQS based on the enabling signal in order to determine a sampling level. The control circuit determines whether the sampling level matches a signal level of the preamble or not.

Abstract: An ODT circuit is connected to a memory module and includes a first transmission line, a first ODT, a second ODT, a first switch circuit, a third ODT, a fourth ODT, a second switch circuit, and an ODT control logic. The first and second ODTs are coupled to a first node on the first transmission line. The first switch circuit includes a first switch and a second switch, and is driven according to the first control signal. The third and the fourth ODTs are coupled to a second node on the first transmission line. The second switch circuit includes a third switch and a fourth switch, and is driven according to the second control signal. The ODT control logic outputs the first control signal and the second control signal to control the first switch circuit and the second switch circuit to be turned on at different timings.

Abstract: A memory controller adjusts impedance matching of an output terminal and outputs a control signal that controls a memory through the output terminal. The memory controller includes a first driving and impedance matching circuit, a second driving and impedance matching circuit, and a logic circuit. The logic circuit, which is coupled to the first driving and impedance matching circuit and the second driving and impedance matching circuit, sets a first impedance and a first driving capability of the first driving and impedance matching circuit, sets a second impedance and a second driving capability of the second driving and impedance matching circuit, and enables the first driving and impedance matching circuit to cause the control signal to have a first level or enables the second driving and impedance matching circuit to cause the control signal to have a second level different from the first level.

Abstract: A memory controller adjusts impedance matching of an output terminal and outputs a control signal that controls a memory through the output terminal. The memory controller includes a first driving and impedance matching circuit, a second driving and impedance matching circuit, and a logic circuit. The logic circuit, which is coupled to the first driving and impedance matching circuit and the second driving and impedance matching circuit, sets a first impedance and a first driving capability of the first driving and impedance matching circuit, sets a second impedance and a second driving capability of the second driving and impedance matching circuit, and enables the first driving and impedance matching circuit to cause the control signal to have a first level or enables the second driving and impedance matching circuit to cause the control signal to have a second level different from the first level.

Abstract: A memory test method is provided that includes the steps outlined below. The memory controller performs data-writing and data-reading on a memory module. When a quantity of read data is incorrect, a data-strobe enable signal is calibrated to perform data reading. When there is one of less than one piece of negative edge data reading content, a sampling unit is triggered. When the quantity of read data increases, the condition that the data-strobe signal is not received is determined. When the quantity does not increase, the memory controller is inspected. When there is more than one piece of read data, the burst mode setting of the memory module is inspected. When the quantity is correct and the content is not correct, a transmission circuit setting and the sampling unit are inspected. When the quantity and the content are correct, the test flow is terminated.

Abstract: A memory control device, which includes a signal generating circuit, a data writing circuit and a repeating circuit. The repeating circuit is coupled to the data writing circuit. The signal generating circuit is configured to generate a data strobe signal and send the data strobe signal to a memory. The data strobe signal comprises a preamble signal. The data writing circuit is configured to write a series of data to the memory according to the data strobe signal. The repeating circuit is configured to repeat a first data of the series of data in a period of the preamble signal.

Abstract: A memory test method is provided that includes the steps outlined below. The memory controller performs data-writing and data-reading on a memory module. When a quantity of read data is incorrect, a data-strobe enable signal is calibrated to perform data reading. When there is one of less than one piece of negative edge data reading content, a sampling unit is triggered. When the quantity of read data increases, the condition that the data-strobe signal is not received is determined. When the quantity does not increase, the memory controller is inspected. When there is more than one piece of read data, the burst mode setting of the memory module is inspected. When the quantity is correct and the content is not correct, a transmission circuit setting and the sampling unit are inspected. When the quantity and the content are correct, the test flow is terminated.

Abstract: A memory control device, which includes a signal generating circuit, a data writing circuit and a repeating circuit. The repeating circuit is coupled to the data writing circuit. The signal generating circuit is configured to generate a data strobe signal and send the data strobe signal to a memory. The data strobe signal comprises a preamble signal. The data writing circuit is configured to write a series of data to the memory according to the data strobe signal. The repeating circuit is configured to repeat a first data of the series of data in a period of the preamble signal.

Abstract: A memory control circuit includes a comparator, an eye width measuring circuit and a calibration circuit, wherein the comparator is arranged to compare a data signal with a reference voltage to generate a compared data signal; the eye width measuring circuit is coupled to the comparator, and is arranged to measure an eye width of the compared data signal to generate a measuring result; and the calibration circuit is coupled to the comparator and the eye width measuring circuit, and is arranged to adjust a level of the reference voltage according to the measuring result.

Abstract: a memory control circuit includes a comparator, an eye width measuring circuit and a calibration circuit, wherein the comparator is arranged to compare a data signal with a reference voltage to generate a compared data signal; the eye width measuring circuit is coupled to the comparator, and is arranged to measure an eye width of the compared data signal to generate a measuring result; and the calibration circuit is coupled to the comparator and the eye width measuring circuit, and is arranged to adjust a level of the reference voltage according to the measuring result.

Abstract: The disclosure provides an electronic device and a control method for the electronic device. The electronic device comprises: a memory unit, a metal pad, and a control unit. The metal pad is coupled to the memory unit, and utilized for receiving a first signal and a second signal. The control unit is coupled to the metal pad, and utilized for generating a control signal during a specific time period to control the first signal and the second signal received by the metal pad, to pull up a level of the first signal and to pull down a level of the second signal during the specific time period, so as to make the first signal and the second signal have a voltage difference. The disclosure can eliminate a glitch and avoid problems caused by inputting the glitch.

Abstract: This invention discloses a memory control circuit and method of controlling a data reading process of a memory module. In the data reading process, the memory module transmits a data signal and a data strobe signal used to recover the data signal. The data strobe signal includes a preamble part. The method includes steps of: controlling an impedance matching circuit of the memory module so that the data strobe signal is kept at a fixed level before the preamble part; generating a clock; generating an enabling signal according to the clock; sampling the data strobe signal according to the enabling signal to generate a sampled result; adjusting an enabling time of the enabling signal according to the sampled result; and starting a data recovering process for the data signal according to the enabling signal.

Abstract: The disclosure provides an electronic device and a control method for the electronic device. The electronic device comprises: a memory unit, a metal pad, and a control unit. The metal pad is coupled to the memory unit, and utilized for receiving a first signal and a second signal. The control unit is coupled to the metal pad, and utilized for generating a control signal during a specific time period to control the first signal and the second signal received by the metal pad, to pull up a level of the first signal and to pull down a level of the second signal during the specific time period, so as to make the first signal and the second signal have a voltage difference. The disclosure can eliminate a glitch and avoid problems caused by inputting the glitch.

Abstract: This invention discloses a memory control circuit and method of controlling a data reading process of a memory module. In the data reading process, the memory module transmits a data signal and a data strobe signal used to recover the data signal. The data strobe signal includes a preamble part. The method includes steps of: controlling an impedance matching circuit of the memory module so that the data strobe signal is kept at a fixed level before the preamble part; generating a clock; generating an enabling signal according to the clock; sampling the data strobe signal according to the enabling signal to generate a sampled result; adjusting an enabling time of the enabling signal according to the sampled result; and starting a data recovering process for the data signal according to the enabling signal.