Abstract: An automatic frequency modulation circuit and an automatic frequency modulation method using efficiency statistics as a reference for frequency modulation applied to a pulse-width modulation (PWM) system are disclosed. The automatic frequency modulation circuit includes an oscillator unit, an on-time generating unit, a frequency adjusting unit and a frequency selecting unit. The oscillator unit receives a reference current and generate a clock signal. The on-time generating unit, coupled to the oscillator unit, receives a reference voltage and a first voltage of the oscillator unit and generates an on-time signal. The frequency adjusting unit, coupled to the on-time generating unit, receives the on-time signal and a PWM signal and generates a frequency adjusting signal. The frequency selecting unit is coupled to the frequency adjusting unit and automatically adjusts an original frequency according to the frequency adjusting signal to generate an adjusted frequency.

Abstract: An automatic frequency modulation circuit and an automatic frequency modulation method using efficiency statistics as a reference for frequency modulation applied to a pulse-width modulation (PWM) system are disclosed. The automatic frequency modulation circuit includes an oscillator unit, an on-time generating unit, a frequency adjusting unit and a frequency selecting unit. The oscillator unit receives a reference current and generate a clock signal. The on-time generating unit, coupled to the oscillator unit, receives a reference voltage and a first voltage of the oscillator unit and generates an on-time signal. The frequency adjusting unit, coupled to the on-time generating unit, receives the on-time signal and a PWM signal and generates a frequency adjusting signal. The frequency selecting unit is coupled to the frequency adjusting unit and automatically adjusts an original frequency according to the frequency adjusting signal to generate an adjusted frequency.

Abstract: A charge pump, applied to an OLED display panel and coupled to an output capacitor, includes a first switch to a tenth switch and a first capacitor to a third capacitor. The first switch and second switch are coupled in series between a first voltage and a second voltage lower than first voltage. The third switch is coupled to second voltage. The sixth switch is coupled to first voltage. The seventh switch is coupled to second voltage. The fourth switch, eighth switch and tenth switch are coupled to output capacitor. The first capacitor is coupled between first switch and second switch. The second capacitor is coupled between fifth switch and sixth switch. The third capacitor is coupled between seventh switch and eighth switch. The charge pump is operated in a first phase, a second-A phase, the first phase and a second-B phase in order to provide negative output voltage.

Abstract: A time multiplexing circuit applied to a DC-DC converting system including first to third NOR gates, first and second inverters, first and second D-type flip-flops, a NAND gate, an OR gate and an AND gate. The first NOR gate and second NOR gate receive the first and second pulse-width modulation signals respectively and output a boost state request signal and a buck-boost state request signal respectively. The first D-type flip-flop outputs a first time multiplex output signal and a first reverse time multiplex output signal. The second D-type flip-flop outputs a second time multiplex output signal and a second reverse time multiplex output signal. The third NOR gate outputs another first time multiplex output signal. The NAND gate outputs another second time multiplex output signal. The OR gate outputs a first reverse output signal. The AND gate outputs a second reverse output signal.

Abstract: A soft-start control circuit includes first to third inverters, first to third comparators, first to fourth resistors, first to fourth D-type flip-flops and a NOR gate. The first comparator outputs a first trigger signal. The second comparator outputs a second trigger signal. The third comparator outputs a third trigger signal. The first D-type flip-flop outputs a first error amplification ready signal. The second D-type flip-flop outputs a second error amplification ready signal. The third D-type flip-flop outputs a high-level output voltage ready signal. The fourth D-type flip-flop outputs a low-level output voltage ready signal. The NOR gate receives an inverted signal of a high-level output voltage enable signal and the third trigger signal and outputs a high-level output voltage control signal to prevent an inrush current of the DC-DC conversion system during a startup process.

Abstract: A bias generation circuit coupled to a display panel is disclosed. The bias generation circuit includes a linear regulator, a charge pump and a synchronous dual mode boost DC-DC converter. The linear regulator and the charge pump are coupled to the display panel respectively. The synchronous dual mode boost DC-DC converter is selectively operated in a pulse width modulation mode or a pulse frequency modulation mode according to a control signal. In the pulse width modulation mode, the synchronous dual mode boost DC-DC converter controls the linear regulator to generate a first voltage signal to the display panel. In the pulse frequency modulation mode, the synchronous dual mode boost DC-DC converter controls the charge pump to generate a second voltage signal to the display panel.

Abstract: A time multiplexing circuit applied to a DC-DC converting system including first to third NOR gates, first and second inverters, first and second D-type flip-flops, a NAND gate, an OR gate and an AND gate. The first NOR gate and second NOR gate receive the first and second pulse-width modulation signals respectively and output a boost state request signal and a buck-boost state request signal respectively. The first D-type flip-flop outputs a first time multiplex output signal and a first reverse time multiplex output signal. The second D-type flip-flop outputs a second time multiplex output signal and a second reverse time multiplex output signal. The third NOR gate outputs another first time multiplex output signal. The NAND gate outputs another second time multiplex output signal. The OR gate outputs a first reverse output signal. The AND gate outputs a second reverse output signal.

Abstract: A soft-start control circuit includes first to third inverters, first to third comparators, first to fourth resistors, first to fourth D-type flip-flops and a NOR gate. The first comparator outputs a first trigger signal. The second comparator outputs a second trigger signal. The third comparator outputs a third trigger signal. The first D-type flip-flop outputs a first error amplification ready signal. The second D-type flip-flop outputs a second error amplification ready signal. The third D-type flip-flop outputs a high-level output voltage ready signal. The fourth D-type flip-flop outputs a low-level output voltage ready signal. The NOR gate receives an inverted signal of a high-level output voltage enable signal and the third trigger signal and outputs a high-level output voltage control signal to prevent an inrush current of the DC-DC conversion system during a startup process.

Abstract: A charge pump, applied to an OLED display panel and coupled to an output capacitor, includes a first switch to a tenth switch and a first capacitor to a third capacitor. The first switch and second switch are coupled in series between a first voltage and a second voltage lower than first voltage. The third switch is coupled to second voltage. The sixth switch is coupled to first voltage. The seventh switch is coupled to second voltage. The fourth switch, eighth switch and tenth switch are coupled to output capacitor. The first capacitor is coupled between first switch and second switch. The second capacitor is coupled between fifth switch and sixth switch. The third capacitor is coupled between seventh switch and eighth switch. The charge pump is operated in a first phase, a second-A phase, the first phase and a second-B phase in order to provide negative output voltage.

Abstract: A LED driving apparatus including a power converter, a judging module and a control module is disclosed. The power converter and the judging module are coupled to at least one LED respectively. The control module is coupled to the judging module. The control module includes a current source and a transconductance amplifier. The current source is coupled to an output terminal of the transconductance amplifier. The power converter converts an input voltage into an output voltage and transmits the output voltage to the at least one LED. The judging module judges whether a LED current is changed from a first LED current value to a second LED current value. If yes, the judging module generates a judging signal to the control module. The control module changes a current value of the current source and a transconductance of the transconductance amplifier.

Abstract: In a LED driver, a dimming control circuit receives a PWM signal and a clock signal and outputs a dimming signal and a sampling signal. A turn-on time of sampling signal is shorter than a cycle of clock signal. A first error amplifier receives a feedback voltage, a reference voltage and a dimming signal and outputs a compensating voltage. A second error amplifier receives the compensating voltage and a ramp signal and outputs a pulse voltage. A driving controller receives the dimming signal and pulse voltage and outputs a control signal. An output stage receives the control signal and an input voltage and generates an output voltage to LED strings. A minimum voltage selecting unit selects a minimum LED voltage. The first error amplifier receives the minimum LED voltage through the selectively conducted switch unit controlled by the sampling signal.

Abstract: A bias generation circuit coupled to a display panel is disclosed. The bias generation circuit includes a linear regulator, a charge pump and a synchronous dual mode boost DC-DC converter. The linear regulator and the charge pump are coupled to the display panel respectively. The synchronous dual mode boost DC-DC converter is selectively operated in a pulse width modulation mode or a pulse frequency modulation mode according to a control signal. In the pulse width modulation mode, the synchronous dual mode boost DC-DC converter controls the linear regulator to generate a first voltage signal to the display panel. In the pulse frequency modulation mode, the synchronous dual mode boost DC-DC converter controls the charge pump to generate a second voltage signal to the display panel.

Abstract: A LED driving apparatus including a power converter, a judging module and a control module is disclosed. The power converter and the judging module are coupled to at least one LED respectively. The control module is coupled to the judging module. The control module includes a current source and a transconductance amplifier. The current source is coupled to an output terminal of the transconductance amplifier. The power converter converts an input voltage into an output voltage and transmits the output voltage to the at least one LED. The judging module judges whether a LED current is changed from a first LED current value to a second LED current value. If yes, the judging module generates a judging signal to the control module.

Abstract: In a LED driver, a diming control circuit receives a PWM signal and a clock signal and outputs a dimming signal and a sampling signal. A turn-on time of sampling signal is shorter than a cycle of clock signal. A first error amplifier receives a feedback voltage, a reference voltage and a dimming signal and outputs a compensating voltage. A second error amplifier receives the compensating voltage and a ramp signal and outputs a pulse voltage. A driving controller receives the dimming signal and pulse voltage and outputs a control signal. An output stage receives the control signal and an input voltage and generates an output voltage to LED strings. A minimum voltage selecting unit selects a minimum LED voltage. The first error amplifier receives the minimum LED voltage through the selectively conducted switch unit controlled by the sampling signal.

Abstract: A position-detecting device is provided. The optical position-detecting device essentially comprises a light-emitting source, a mask, and a light-detecting device, in which a plurality of grating-holes are provided on the mask for allowing of a projecting light source, generated by the light-emitting source, to pass therethrough, and the projecting light source passing through the grating-holes are then absorbed by a plurality of light-detecting element provided on the light-detecting device. Each light-detecting device is provided as a non-rectangular mode, while an interval space is existed between any two of adjacent light-detecting elements. The partially active area of one of the light-detecting elements is naturally provided at the vertical extension of the interval space, and thus diminishing disadvantages of misdetermination and low sensitivity of the light-detecting device induced by the presence of an interval space.