Abstract: An imaging lens module includes a lens element having an optical axis, a lens carrier and a variable through hole assembly. The lens carrier accommodates the lens element and sequentially includes an object-side portion, an image-side portion and a tubular portion. The object-side portion configured for light entering the imaging lens module forms a minimum opening of the lens carrier. The variable through hole assembly is disposed on the object-side portion and includes rotatable blades rotatably disposed about the optical axis and configured to form a through hole with a variable size. Moreover, the object-side portion further has a guiding structure guiding the movement of the rotatable blades and located further away from the optical axis than the minimum opening. Moreover, the object-side portion and the image-side portion form an air sleeve therebetween, and the air sleeve is located further away from the optical axis than the tubular portion.

Abstract: A method for manufacturing a semiconductor device includes forming a first dielectric layer over a semiconductor fin. The method includes forming a second dielectric layer over the first dielectric layer. The method includes exposing a portion of the first dielectric layer. The method includes oxidizing a surface of the second dielectric layer while limiting oxidation on the exposed portion of the first dielectric layer.

Abstract: A rotary device with automatic reset function for precise stopping and holding of a viewable rotating element without free play or slop remaining includes a conversion assembly, and a power assembly with output element and sensing assembly. The conversion assembly comprises a light-shielding structure with the light-shielding structure on the extension part. The power assembly with output element can drive the extension part to rotate synchronously with the light-shielding structure. The detachable sensing assembly overlaps the rotation path of the light-shielding structure, and the conversion assembly rotates at different angles so that the light-shielding structure and the sensing assembly will match at certain angles, so as to trigger a sensing signal and call up the output element. A display screen includes the rotary device with automatic reset function and a display assembly.

Abstract: A semiconductor device includes a substrate having a major surface. The semiconductor device includes a dielectric material having a uniform thickness on the major surface of the substrate. The semiconductor device includes a first plurality of fins extending from the major surface of the substrate, wherein each fin of the first plurality of fins has a first height from the major surface of the substrate. The semiconductor device includes a second plurality of fins extending from the major surface of the substrate, wherein a first fin of the second plurality of fins is on a first side of the first plurality of fins, a second fin of the second plurality of fins is on a second side of the first plurality of fins opposite the first side, each fin of the second plurality of fins has a second height different from the first height.

Abstract: A structure includes first and second active areas, first and second gates and a data line. The first gate is continuous and crosses over the first active area and the second active area. The first gate corresponds to gate terminals of first and second transistors, and first source/drain regions of the first and the second active areas correspond to first source/drain terminals of the first and second transistors. The second gate includes first and second gate portions electrically isolated from each other. The first and second gate portions correspond to gate terminals of third and fourth transistors, respectively. The first gate portion crosses over the first active area, and the second gate portion crosses over the second active area. The first data line is coupled to the first source/drain regions of the first active area and the second active area.

Abstract: A switching converter having pulse skipping mode includes a power stage circuit, a feedback control circuit, an operating signal generator circuit and a pulse skipping circuit. The feedback control circuit generates an initial pulse width modulation (PWM) signal according the output power. The operating signal generator circuit masks a part of pulses of a clock signal according to a pulse width of a pulse skipping signal, so as to generate an adjusted PWM signal. The pulse skipping circuit adaptively generates a duty ratio signal according to an input voltage and an output voltage, so as to generate the pulse skipping reference signal related to a duty ratio of the initial PWM signal. The pulse skipping circuit compares an amplification signal with the pulse skipping reference signal to generate the pulse skipping signal. The power stage circuit converts the input power to the output power according to the adjusted PWM signal.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The semiconductor device structure includes a spacer over a side of the gate stack. The semiconductor device structure includes a dielectric layer over the substrate. The dielectric layer has a first recess, the dielectric layer has an upper portion and a first lower portion, the upper portion is over the first recess, the first recess is between the first lower portion and the spacer, and the upper portion has a convex curved sidewall.

Abstract: An electronic device includes a first insulating layer, a first conductive portion, a second conductive portion, a transistor, and an electronic unit. The first insulating layer has a first opening penetrating the first insulating layer along a first direction. The first conductive portion is disposed in the first opening. The second conductive portion is electrically connected to the first conductive portion. The transistor is electrically connected to the second conductive portion. The electronic unit is electrically connected to the first conductive portion. In a cross-sectional view of the electronic device, the electronic unit and the second conductive portion are disposed on two opposite sides of the first insulating layer respectively, the first conductive portion has a first length along a second direction perpendicular to the first direction, the second conductive portion has a second length along the second direction, and the first length is different from the second length.

Abstract: A composition and a method for preparing the same are provided. The method for preparing the composition includes providing a polyethylene terephthalate waste. The polyethylene terephthalate waste is subjected to a depolymerization in the presence of a catalyst and an alcoholysis agent to obtain a mixture, wherein an oxidizing atmosphere is continuously introduced into the depolymerization. The mixture is subjected to a solid-liquid separation to obtain a solid. The solid is subjected to a purification to obtain the composition.

Abstract: A mobile device with communication and sensing functions includes a first radiation element, a second radiation element, a third radiation element, a fourth radiation element, a capacitor, a first metal element, a second metal element, a third metal element, a nonconductive support element, and a proximity sensor. The first metal element is coupled through the capacitor to a ground voltage. The second metal element is coupled to the first metal element. The third metal element is coupled to the first metal element. The third metal element and the second metal element substantially extend in opposite directions. The proximity sensor is coupled to the capacitor and the first metal element. A hybrid antenna structure is formed by a first radiation element, a second radiation element, a third radiation element, a fourth radiation element, a first metal element, a second metal element, and a third metal element.

Abstract: A motorcycle head-up display (HUD) applicable to a motorcycle is provided. The motorcycle includes a motorcycle head and an electronic control unit. The HUD includes a display lens, a driving module, a projecting module, and a controller. The display lens is disposed on an upper surface of the motorcycle head. The driving module is configured to control a height of the display lens respective to the upper surface. The projecting module is disposed inside an accommodating space of the motorcycle head and configured to output a projecting image onto the display lens. The controller is connected to the projecting module and the driving module and configured to retrieve riding information of the motorcycle from the electronic control unit and generate a first command according to the riding information. The driving module is configured to control a movement of the display lens according to the first command.

Abstract: An OTP memory cell is provided. The OTP memory cell includes: an antifuse transistor, wherein a gate terminal of the antifuse transistor is connected to a first word line having a first signal, and the antifuse transistor is selectable between a first state and a second state in response to the first signal; and a selection transistor connected between the antifuse transistor and a bit line, wherein a gate terminal of the selection transistor is connected to a second word line having a second signal, and the selection transistor is configured to provide access to the antifuse transistor in response to the second signal. A first terminal of the antifuse transistor is a vacancy terminal, and a second terminal of the antifuse transistor is connected to the selection transistor.

Abstract: An electronic device includes a heater, and a sampling and holding circuit coupled to the heater. The sampling and holding circuit includes a sampling unit, a register unit and a feedback unit. The sampling unit is for receiving a data signal. The register unit has an input terminal and an output terminal. The input terminal is coupled to the sampling unit, and the output terminal is for outputting a first signal. The feedback unit is coupled to the input terminal and the output terminal of the register unit. When the feedback unit is turned on, the feedback unit feeds the first signal to the input terminal.

Abstract: An integrated circuit (IC) device includes a first active region extending along a first direction, a first pair of gate regions extending across the first active region along a second direction transverse to the first direction, and a first metal layer. The first pair of gate regions and the first active region configure a first program transistor and a first read transistor sharing a common source/drain region. The first metal layer includes a first program word line pattern over and coupled to the gate region of the first program transistor, a first read word line pattern over and coupled to the gate region of the first read transistor, a first source line pattern coupled to another source/drain region of the first program transistor, and a first bit line pattern coupled to another source/drain region of the first read transistor.

Abstract: Disclosed herein are related to a memory array. In one aspect, the memory array includes a set of resistive storage circuits including a first subset of resistive storage circuits connected between a first local line and a second local line in parallel. The first local line and the second local line may extend along a first direction. In one aspect, for each resistive storage circuit of the first subset of resistive storage circuits, current injected at a first common entry point of the first local line exits through a first common exit point of the second local line, such that each resistive storage circuit of the first subset of resistive storage circuits may have same or substantial equal resistive loading.

Abstract: The present disclosure relates to an integrated chip in some embodiments. The integrated chip includes a memory device disposed over a lower interconnect within one or more lower inter-level dielectric (ILD) layers over a substrate. An upper ILD layer laterally surrounds the memory device. An etch stop layer is disposed along a sidewall of the memory device and over an upper surface of the one or more lower ILD layers. An upper interconnect is arranged along opposing sides of the memory device. The upper interconnect rests of an upper surface of the etch stop layer. The upper surface of the etch stop layer is vertically below a top of the memory device.

Abstract: A memory device includes a plurality of arrays coupled in parallel with each other. A first array of the plurality of arrays includes a first switch and a plurality of first memory cells that are arranged in a first column, a second switch and a plurality of second memory cells that are arranged in a second column, and at least one data line coupled to the plurality of first memory cells and the plurality of second memory cells. The second switch is configured to output a data signal from the at least one data line to a sense amplifier.

Abstract: A memory system includes a memory array comprising a plurality of memory cells. Each of the memory cells includes a first programming transistor, a second programming transistor, a first reading transistor coupled to the first programming transistor in series, and a second reading transistor coupled to the second programming transistor in series. The memory system includes an authentication circuit operatively coupled to the memory array. The authentication circuit is configured to generate a Physically Unclonable Function (PUF) signature based on respective logic states of the plurality of memory cells. The logic state of each of the plurality of memory cells is determined based on a preceding breakdown of either the corresponding first programming transistor or second programming transistor.

Abstract: A mobile device for reducing SAR (Specific Absorption Rate) includes a first radiation element, a second radiation element, a third radiation element, and a dielectric substrate. The first radiation element has a feeding point. The second radiation element is adjacent to the first radiation element. The second radiation element has a first notch region, a second notch region, and a third notch region. The second radiation element is coupled through the third radiation element to a ground voltage. The first radiation element, the second radiation element, and the third radiation element are disposed on the dielectric substrate. An antenna structure is formed the first radiation element, the second radiation element, and the third radiation element.

Abstract: A memory device includes a plurality of memory cells including a first memory cell and a second memory cell, a first bit line connected to the first memory cell, a second bit line connected to the second memory cell, a first word line connected to the first and second memory cells, a first control transistor connected to the first bit line, a second control transistor connected to second bit line, a first mux transistor commonly connected to the first and second control transistors, and a sense amplifier connected to the first mux transistor.