Abstract: The present disclosure provides a semiconductor device and an electrostatic discharge (ESD) clamp circuit. The semiconductor device includes a voltage divider, a cascoded inverter, and a discharge circuit. The voltage divider is electrically coupled between a power supply voltage and an output voltage of the semiconductor device. The cascoded inverter is electrically coupled to the voltage divider. The discharge circuit is electrically coupled to the cascoded inverter. The cascoded inverter is configured to turn on the discharge circuit o discharge an electrostatic discharge (ESD) current in response to an ESD event occurring on the power supply voltage or the output voltage when the semiconductor device is in an ESD mode.

Abstract: A semiconductor device includes anti-fuse cells. The anti-fuse cells include a first active area, a first gate, a second gate, at least one first gate via, and at least one second gate via. The first gate and the second gate are separate from each other. The first gate and the second gate extend to cross over the first active area. The at least one first gate via is coupled to the first gate and disposed directly above the first active area. The at least one second gate via is coupled to the second gate. The first gate is coupled through the at least one first gate via to a first word line for receiving a first programming voltage, and the second gate is coupled through the at least one second gate via to a second word line for receiving a first reading voltage.

Abstract: A method of operating a memory circuit includes turning on a first programming device and turning on a first selection device thereby causing a first current to flow through a first fuse element. The first fuse element is coupled between the first selection device and the first programming device. The method further includes turning off a second programming device and turning off a second selection device, and blocking the first current from flowing through a second fuse element that is coupled between the second selection device and the first programming device.

Abstract: A control signal transmission device for a quantum computer is provided. The control signal transmission device includes a laser source, a digital-to-analog converter (DAC), an electro-optic modulation circuit, an optical fiber, an optic-electro demodulation circuit and a plurality of qubits. The laser source provides a light. The DAC provides a plurality of first control signals. The electro-optic modulation circuit integrates the corresponding first control signals into the light to generate an optical signal, and provides the optical signal to the optical fiber. The optic-electro demodulation circuit converts and splits the optical signal into a plurality of second control signals. The optic-electro demodulation circuit transmits the second control signals to the corresponding qubits. The qubits are controlled by the corresponding second control signals. An ambient temperature set by the optic-electro demodulation circuit and the qubits is much lower than a preset temperature value.

Abstract: A method for operating a memory device is provided. A first address is decoded to select a bit line of a memory device. A second address is decoded to select a word line of the memory device. A word line voltage is applied to the selected word line. A bit line voltage is applied to the selected bit line. A first bias voltage is applied to each of a plurality of unselected word lines connected to a plurality of memory cells connected to the selected bit line san a memory cell connected to both the selected bit line and the selected word line.

Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a first memory cell and a second memory cell over a substrate, wherein each of the first and second memory cells comprises a bottom electrode, a resistance switching element over the bottom electrode, and a top electrode over the resistance switching element; depositing a first dielectric layer over the first and second memory cells, such that the first dielectric layer has a void between the first and second memory cells; depositing a second dielectric layer over the first dielectric layer; and forming a first conductive feature and a second conductive feature in the first and second dielectric layers and respectively connected with the top electrode of the first memory cell and the top electrode of the second memory cell.

Abstract: A device includes a memory cell that randomly presents either a first logic state or a second logic state. The memory cell includes: a plurality of first nanostructures extending along a first lateral direction; a plurality of second nanostructures extending along the first lateral direction and disposed at a first side of the plurality of first nanostructures; a plurality of third nanostructures extending along the first lateral direction and disposed at a second side of the plurality of first nanostructures; a dielectric fin structure disposed immediately next to the plurality of first nanostructures along a second lateral direction, wherein a first sidewall of each of the plurality of first nanostructures facing toward or away from the second lateral direction is in contact with the dielectric fin structure; and a first gate structure wrapping around each of the plurality of first nanostructures except for the first sidewall.

Abstract: A wireline cable includes an electrically conductive cable core for transmitting electrical power. The wireline cable further includes an inner layer of a plurality of first armor wires surrounding the cable core and an outer layer of a plurality of second armor wires surrounding the inner layer, wherein a diameter of the outer layer of the plurality of second armor wires is smaller than a diameter of the inner layer of the plurality of first armor wires.

Abstract: A waterborne autonomous rescue device floats in a body of water and continuously senses an ambient audio in the body of water, and performs voice recognition on the ambient audio to recognize a cry-out-for-help voice, and calculates a direction of an emission source (e.g. a drowning person) that emits the cry-out-for-help voice, and then the waterborne autonomous rescue device will automatically move forward in the direction of the emission source, so that the drowning person can cling to the waterborne autonomous rescue device and be carried to a safe location; a waterborne autonomous rescue system includes the waterborne autonomous rescue device which is further connected to a monitoring device; a monitoring personnel can check the status of the waterborne autonomous rescue device through the monitoring device. When a drowning incident occurs, the monitoring personnel can go to a location of the waterborne autonomous rescue device to carry out subsequent rescue.

Abstract: A voltage provision circuit includes a first NMOS transistor gated with a first control signal and sourced with a ground voltage, a second NMOS transistor gated with a second control signal complementary to the first control signal and sourced with the ground voltage, a first PMOS transistor sourced with a first supply voltage, a second PMOS transistor sourced with the first supply voltage, and a voltage modulation circuit that is coupled between the first to second PMOS transistors and the first to second NMOS transistors, and is configured to provide a first intermediate signal based on the first and second control signals. The first intermediate signal has a first logic state corresponding to the first supply voltage and a second logic state corresponding to a second supply voltage that is a fraction of the first supply voltage.

Abstract: Fracturing equipment includes: a plunger pump, a main motor and a noise reduction device. The plunger pump is used for pressurizing liquid. The main motor is connected to the plunger pump by transmission for providing driving force to the plunger pump. The noise reduction device is constructed as a cabin structure and covers outside the main motor and isolates the main motor from the plunger pump. With the fracturing equipment according to the present disclosure, the fracturing equipment is driven by the main motor with relatively low noise during operation. The noise reduction device isolates the main motor from the outside, which can effectively reduce the noise intensity transmitted to the outside during operation, thereby achieve the effect of noise reduction. In addition, the plunger pump is isolated from the main motor by the noise reduction device, thus realizing isolation of high-pressure dangerous areas and ensuring safe operation.

Abstract: A method for cleaning is provided. The method includes: removing a pellicle frame from a top surface of a photomask by debonding an adhesive between the photomask and the pellicle frame, wherein a first portion of the adhesive is remained on the top surface of the photomask, and removing the first portion of the adhesive on the top surface of the photomask, including applying an alkaline solution to the top surface of the photomask, and performing a mechanical impact to the photomask.

Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.

Abstract: A mobile device supporting wideband operations includes a first metal mechanism element, a dielectric substrate, a first feeding radiation element, a second feeding radiation element, a ground element, and a second metal mechanism element. The first metal mechanism element includes a main portion and a sidewall portion. The sidewall portion of the first metal mechanism element has a first slot. Both the first feeding radiation element and the second feeding radiation element extend across the first slot of the first metal mechanism element. An antenna structure is formed by the first slot of the first metal mechanism element, the dielectric substrate, the first feeding radiation element, the second feeding radiation element, and the ground element. The second metal mechanism element is disposed opposite to the main portion of the first metal mechanism element. The second metal mechanism element has a second slot.

Abstract: A turbine engine cleaning system is disclosed. In the turbine engine cleaning system, a temperature sensor obtains a temperature within a combustion chamber of the turbine engine; a cleaning agent storage device stores cleaning agent; a cleaning agent delivery device is connected between the cleaning agent storage device and the combustion chamber of the turbine engine, and includes a pipe and a driver mechanism; the pipe includes a front-end pipe and a rear-end pipe; the front-end pipe is connected to the cleaning agent storage device; the rear-end pipe is connected to the front-end pipe and the combustion chamber; the driver mechanism is connected to the front-end pipe and drives the cleaning agent to enter the combustion chamber from the cleaning agent storage device by the front-end pipe and the rear-end pipe to clean components when the temperature within the combustion chamber is less than or equal to a predetermined temperature.

Abstract: A memory device includes a plurality of memory cells including a first memory cell and a second memory cell, a first bit line connected to the first memory cell, a second bit line connected to the second memory cell, a first word line connected to the first and second memory cells, a first control transistor connected to the first bit line, a second control transistor connected to second bit line, a first mux transistor commonly connected to the first and second control transistors, and a sense amplifier connected to the first mux transistor.

Abstract: A multi-fuse memory cell is disclosed. The circuit includes: a first fuse element electrically coupled to a first transistor, a gate of the first transistor is electrically coupled to a first selection signal; a second fuse element electrically coupled to a second transistor, a gate of the second transistor is electrically coupled to a second selection signal, both the first transistor and the second transistor are grounded; and a programming transistor electrically coupled to the first fuse element and the second fuse element, wherein a gate of the programming transistor is electrically coupled to a programming signal.

Abstract: A memory cell is disclosed. The memory cell includes a first transistor. The first transistor includes a first conduction channel collectively constituted by one or more first nanostructures spaced apart from one another along a vertical direction. The memory cell includes a second transistor electrically coupled to the first transistor in series. The second transistor includes a second conduction channel collectively constituted by one or more second nanostructures spaced apart from one another along the vertical direction. At least one of the one or more first nanostructures is applied with first stress by a first metal structure extending, along the vertical direction, into a first drain/source region of the first transistor.

Abstract: A semiconductor device includes a memory cell including a first transistor, a second transistor, and a resistor. Each of the first transistor and the second transistor is operatively coupled to the resistor in series. The second transistor is formed below the resistor such that the second transistor provides heat to the resistor when the memory cell is being programmed.

Abstract: A memory device including a substrate, a sense amplifier that includes first gate-all-around transistors that have first drain/source regions that extend into the substrate, and bit cells that include fuse memory elements and second gate-all-around transistors. Each of the bit cells includes a fuse memory element having a first terminal connected to an input of the sense amplifier and a second terminal connected to a second gate-all-around transistor that includes second drain/source regions and a bottom dielectric isolation layer under the second drain/source regions.