Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.

Abstract: Embodiments provide a method of performing a carrier switch for a device wafer, attaching a second wafer and removing a first wafer. A buffer layer is deposited over the device wafer, buffer layer reducing the topography of the surface of the device wafer. After the carrier switch a film-on-wire layer is removed from the buffer layer and then the buffer layer is at least in part removed.

Abstract: A first polymer layer is formed across a package region and a test region. A first metal pattern is formed in the package region and a first test pattern is simultaneously formed in the test region. The first metal pattern has an upper portion located on the first polymer layer and a lower portion penetrating through the first polymer layer, and the first test pattern is located on the first polymer layer and has a first opening exposing the first polymer layer. A second polymer layer is formed on the first metal pattern in the package region and a second test pattern is simultaneously formed on the first test pattern in the test region. The second polymer layer has a second opening exposing the upper portion of the first metal pattern, and the second test pattern has a third opening greater than the first opening of the first test pattern.

Abstract: A method of fabricating a poly silicon layer comprising the following steps is provided. First, a substrate is provided and an amorphous silicon layer is formed on the substrate. A patterned metal layer is formed on the amorphous silicon layer. Next, a pulsed rapid thermal annealing process is performed to form a metal silicide between the patterned metal layer and the amorphous silicon layer, wherein the patterned metal layer and the amorphous silicon layer are adopted for conducting thermal energy to the amorphous silicon layer such that the amorphous silicon layer is converted into a polysilicon layer. Finally, the patterned metal layer is removed. A polysilicon layer formed according to the above-mentioned fabrication method is also provided. The grains of the poly silicon layer are spherical in shape.

Abstract: A method of fabricating a poly silicon layer comprising the following steps is provided. First, a substrate is provided and an amorphous silicon layer is formed on the substrate. A patterned metal layer is formed on the amorphous silicon layer. Next, a pulsed rapid thermal annealing process is performed to form a metal silicide between the patterned metal layer and the amorphous silicon layer, wherein the patterned metal layer and the amorphous silicon layer are adopted for conducting thermal energy to the amorphous silicon layer such that the amorphous silicon layer is converted into a polysilicon layer. Finally, the patterned metal layer is removed. Accordingly, the above processes may prevent the poly silicon layer from metal contamination.

Abstract: A method of fabricating a poly silicon layer comprising the following steps is provided. First, a substrate is provided and an amorphous silicon layer is formed on the substrate. A patterned metal layer is formed on the amorphous silicon layer. Next, a pulsed rapid thermal annealing process is performed to form a metal silicide between the patterned metal layer and the amorphous silicon layer, wherein the patterned metal layer and the amorphous silicon layer are adopted for conducting thermal energy to the amorphous silicon layer such that the amorphous silicon layer is converted into a polysilicon layer. Finally, the patterned metal layer is removed. Accordingly, the above processes may prevent the poly silicon layer from metal contamination.

Abstract: The present invention provides a method for improving the adhesion capability between the ?-type bus electrode and ITO (indium tin oxide) transparent conductive layer. The method includes an ITO transparent conductive layer as an ITO electrode is formed on the glass substrate by sputtering method. Then, a photoresist layer with a cavity pattern is formed on the portion of the ITO transparent conductive film. Next, an etching process is used to remove portion of the ITO transparent conductive film to form a cavity within the ITO transparent conductive film. Then, after removing the photoresist layer, a silver paste as a bus electrode is formed on the glass substrate and on the ITO transparent conductor film to form a pi (?) type bus electrode by print method.

Abstract: A discharge electrode structure of a plasma display panel is described. The discharge electrode structure includes a plurality of expanding electrodes or expanding portions that each one has a symmetric structure. The expanding electrodes are alternately coupled to a pair of conductive electrodes that are on the edge of a plurality of luminant cells in one row. Therefore, oblique symmetric electrodes are disposed at opposite corner location of each luminant cell.

Abstract: The present invention provides a method for improving the adhesion capability between the &pgr;-type bus electrode and ITO (indium tin oxide) transparent conductive layer. The method includes an ITO transparent conductive layer as an ITO electrode is formed on the glass substrate by sputtering method. Then, a photoresist layer with a cavity pattern is formed on the portion of the ITO transparent conductive film. Next, an etching process is used to remove portion of the ITO transparent conductive film to form a cavity within the ITO transparent conductive film. Then, after removing the photoresist layer, a silver paste as a bus electrode is formed on the glass substrate and on the ITO transparent conductor film to form a pi (&pgr;) type bus electrode by print method.

Abstract: A discharge electrode structure of a plasma display panel is described. The discharge electrode structure includes a plurality of expanding electrodes or expanding portions that each one has a symmetric structure. The expanding electrodes are alternately coupled to a pair of conductive electrodes that are on the edge of a plurality of luminant cells in one row. Therefore, oblique symmetric electrodes are disposed at opposite corner location of each ruminant cell.

Abstract: A barrier rib structure for a plasma display panel is described. The barrier rib structure formed on a back substrate has a plurality of parallel barrier ribs. Each barrier rib has a plurality of discharge spaces therein divided by separate walls. Each of the discharge spaces is connected to a small gas channel beside the barrier rib through a small connect opening.

Abstract: A barrier rib structure for a plasma display panel is described. The barrier rib structure formed on a back substrate has a plurality of parallel barrier ribs. Each barrier rib has a plurality of nodes composed of two side-expanded trapezoid bulges. The barrier ribs are arranged according to the nodes to form a plurality of discharge spaces between the barrier ribs and a plurality of gas channels between the nodes to connect the discharge space.

Abstract: A barrier rib structure for a plasma display panel is described. According to the present invention, horizontal barrier ribs having different widths are located parallel to each other. A plurality of perpendicular barrier ribs is used to divide adjacent horizontal barrier ribs into a plurality of discharge spaces. The different width horizontal barrier ribs cause different heights for horizontal barrier ribs during the sintering process. Therefore, gas passages are formed between the barrier ribs and the upper substrate when the upper and the down substrate are sealed together.

Abstract: A high efficiency electrode structure for a plasma display panel is described. The high efficiency electrode structure mainly comprises a comb electrode which including a main line across luminant units in row and a plurality of branches perpendicularly expanded from the main line and located between the luminant units. A transparent electrode parallel to the main line of the comb electrode is coupled to the end of the branches of the comb electrode. The end of the branches approximates the discharge center of the luminant units. The discharge electric field of luminant unit is more uniform and the sustaining voltage is lowered.

Abstract: A barrier rib structure for a plasma display panel is described. The barrier rib structure formed on a back substrate has a plurality of parallel barrier ribs. Each barrier rib has a plurality of nodes composed of two side-expanded trapezoid bulges. The barrier ribs are arranged according to the nodes to form a plurality of discharge spaces between the barrier ribs and a plurality of gas channels between the nodes to connect the discharge space.

Abstract: A barrier rib structure for a plasma display panel is described. The barrier rib structure formed on a back substrate has a plurality of parallel barrier ribs. Each barrier rib has a plurality of discharge spaces therein divided by separate walls. Each of the discharge spaces is connected to a small gas channel beside the barrier rib through a small connect opening.

Abstract: In an alternating current discharge type plasma display panel (PDP) a plurality of parallel barrier walls are formed on a top surface of a back substrate of the PDP and barrier walls are disposed corresponding to cross-points of X electrodes and Y electrodes on a front substrate of the PDP. A structure includes a plurality of discharge cells between the adjacent barrier walls having smaller width corresponding to the X and Y electrodes for forming a large first space, a plurality of non-discharge cells each between the adjacent discharge cells for forming a small second space served as a gas channel between the adjacent discharge cells, and a junction between one discharge cell and the adjacent non-discharge cell, such that energy released from a gas discharge in the discharge cells is concentrated within the discharge cells for increasing discharge efficiency.

Abstract: In an alternating current discharge type plasma display panel (PDP) a plurality of parallel barrier walls are formed on top surface of a back substrate of the PDP and barrier walls are disposed corresponding to cross-points of X electrodes and Y electrodes on a front substrate the PDP. A structure comprises a plurality of discharge cells between the adjacent barrier walls having smaller width corresponding to the X and Y electrodes for forming a large first space, a plurality of non-discharge cells each between the adjacent discharge cells for forming a small second space served as a gas channel between the adjacent discharge cells, and a junction between one discharge cell and the adjacent non-discharge cell, whereby energy released from a gas discharge in the discharge cells is concentrated within the discharge cells for increasing discharge efficiency.

Abstract: In a plasma display panel (PDP) a method for prolonging useful life thereof comprises the steps of performing an experiment on red, green, and blue phosphor layers each coated on a corresponding discharge cell for calculating a gain per gray scale on the phosphor layer of each discharge cell and obtaining expressions to represent relationship with respect to the use time of each discharge cell, thereby establishing a comparison table with respect to the gains; enabling a control circuit of PDP to select one of the gains from the comparison table based on use time for dynamically adjusting strength of input video signal of each discharge cell; and compensating a reduced brightness per gray scale on the phosphor layer of each discharge cell due to increase of the use time by each of emitted red, green and blue lights. This compensates the reduced emissivity and eliminates adverse effects such as shortening of life, color temperature change, and color deviation caused by the reduced emissivity.