Patents by Inventor Sheng Chiang Hung
Sheng Chiang Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230035580Abstract: An interconnect structure and methods of forming the same are described. In some embodiments, the structure includes a first intermetal dielectric (IMD) layer disposed over a plurality of conductive features and a first passive component disposed on the first IMD layer in a first region of the substrate. The structure further includes a second passive component disposed on the first IMD layer in a second region of the substrate. The second passive component includes a first conductive layer, and the first conductive layer has a first thickness. The structure further includes a second IMD layer disposed on the first passive component in the first region and on the second passive component and a portion of the first IMD layer in the second region. The second IMD layer has a second thickness ranging from about five times to about 20 times the first thickness.Type: ApplicationFiled: January 25, 2022Publication date: February 2, 2023Inventors: Yao-Jen TSAI, Chih-Fu CHANG, Sheng Chiang HUNG, Chin-Yuan KO
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Patent number: 10153355Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a substrate, a fin structure, a metal gate and a first polysilicon strip. The fin structure is on the substrate. The metal gate is over the fin structure and is substantially perpendicular to the fin structure. The first polysilicon strip is at a first edge of the fin structure and is substantially parallel to the metal gate.Type: GrantFiled: December 4, 2015Date of Patent: December 11, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Sheng Chiang Hung, Tsung-Che Lu, Chih-Fu Chang
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Publication number: 20170162667Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a substrate, a fin structure, a metal gate and a first polysilicon strip. The fin structure is on the substrate. The metal gate is over the fin structure and is substantially perpendicular to the fin structure. The first polysilicon strip is at a first edge of the fin structure and is substantially parallel to the metal gate.Type: ApplicationFiled: December 4, 2015Publication date: June 8, 2017Inventors: SHENG CHIANG HUNG, TSUNG-CHE LU, CHIH-FU CHANG
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Patent number: 9362399Abstract: The present disclosure relates to methods for fabricating a field-effect transistor. The method includes performing a pocket implantation to a semiconductor substrate; thereafter forming a polysilicon layer on the semiconductor substrate; and patterning the polysilicon layer to form a polysilicon gate. The field-effect transistor (FET) includes a well of a first type dopant, formed in a semiconductor substrate; a metal gate disposed on the semiconductor substrate and overlying the well; a channel formed in the semiconductor substrate and underlying the metal gate; source and drain regions of a second type dopant opposite from the first type, the source and drain regions being formed in the semiconductor substrate and on opposite sides of the channel; and a pocket doping profile of the first type dopant and being defined in the well to form a continuous and uniform doping region from the source region to the drain region.Type: GrantFiled: January 20, 2015Date of Patent: June 7, 2016Assignee: Taiwn Semiconductor Manufacturing Company, Ltd.Inventors: Sheng Chiang Hung, Huai-Ying Huang, Ping-Wei Wang
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Publication number: 20150155382Abstract: The present disclosure relates to methods for fabricating a field-effect transistor. The method includes performing a pocket implantation to a semiconductor substrate; thereafter forming a polysilicon layer on the semiconductor substrate; and patterning the polysilicon layer to form a polysilicon gate. The field-effect transistor (FET) includes a well of a first type dopant, formed in a semiconductor substrate; a metal gate disposed on the semiconductor substrate and overlying the well; a channel formed in the semiconductor substrate and underlying the metal gate; source and drain regions of a second type dopant opposite from the first type, the source and drain regions being formed in the semiconductor substrate and on opposite sides of the channel; and a pocket doping profile of the first type dopant and being defined in the well to form a continuous and uniform doping region from the source region to the drain region.Type: ApplicationFiled: January 20, 2015Publication date: June 4, 2015Inventors: Sheng Chiang Hung, Huai-Ying Huang, Ping-Wei Wang
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Patent number: 8947900Abstract: SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor.Type: GrantFiled: May 22, 2014Date of Patent: February 3, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Huai-Ying Huang, Yu-Kuan Lin, Sheng Chiang Hung, Feng-Ming Chang, Jui-Lin Chen, Ping-Wei Wang
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Patent number: 8940589Abstract: The present disclosure relates to methods for fabricating a field-effect transistor. The method includes performing a pocket implantation to a semiconductor substrate; thereafter forming a polysilicon layer on the semiconductor substrate; and patterning the polysilicon layer to form a polysilicon gate. The field-effect transistor (FET) includes a well of a first type dopant, formed in a semiconductor substrate; a metal gate disposed on the semiconductor substrate and overlying the well; a channel formed in the semiconductor substrate and underlying the metal gate; source and drain regions of a second type dopant opposite from the first type, the source and drain regions being formed in the semiconductor substrate and on opposite sides of the channel; and a pocket doping profile of the first type dopant and being defined in the well to form a continuous and uniform doping region from the source region to the drain region.Type: GrantFiled: May 28, 2010Date of Patent: January 27, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng Chiang Hung, Huai-Ying Huang, Ping-Wei Wang
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Patent number: 8908409Abstract: SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor.Type: GrantFiled: May 22, 2014Date of Patent: December 9, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Huai-Ying Huang, Yu-Kuan Lin, Sheng Chiang Hung, Feng-Ming Chang, Jui-Lin Chen, Ping-Wei Wang
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Publication number: 20140254248Abstract: SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor.Type: ApplicationFiled: May 22, 2014Publication date: September 11, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Huai-Ying Huang, Yu-Kuan Lin, Sheng Chiang Hung, Feng-Ming Chang, Jui-Lin Chen, Ping-Wei Wang
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Publication number: 20140254249Abstract: SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor.Type: ApplicationFiled: May 22, 2014Publication date: September 11, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Huai-Ying Huang, Yu-Kuan Lin, Sheng Chiang Hung, Feng-Ming Chang, Jui-Lin Chen, Ping-Wei Wang
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Patent number: 8743579Abstract: SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor.Type: GrantFiled: April 17, 2013Date of Patent: June 3, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Huai-Yang Huang, Yu-Kuan Lin, Sheng Chiang Hung, Feng-Ming Chang, Jui-Lin Chen, Ping-Wei Wang
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Patent number: 8624327Abstract: A SRAM device with metal gate transistors is provided. The SRAM device includes a PMOS structure and an NMOS structure over a substrate. Each of the PMOS and the NMOS structure includes a p-type metallic work function layer and an n-type metallic work function layer. The p-type work metallic function layer and the n-type metallic work function layer form a combined work function for the PMOS and the NMOS structures.Type: GrantFiled: December 10, 2012Date of Patent: January 7, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng Chiang Hung, Huai-Ying Huang, Ping-Wei Wang
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Publication number: 20130320522Abstract: An embodiment is a semiconductor device comprising a contact pad over a substrate, wherein the contact pad is disposed over an integrated circuit on the substrate and a first passivation layer over the contact pad. A first via in the first passivation layer, wherein the first via has more than four sides, and wherein the first via extends to the contact pad.Type: ApplicationFiled: May 30, 2012Publication date: December 5, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Feng-Liang Lai, Kai-Yuan Yang, Chia-Jen Leu, Sheng Chiang Hung
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Publication number: 20130250660Abstract: SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor.Type: ApplicationFiled: April 17, 2013Publication date: September 26, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Huai-Ying Huang, Yu-Kuan Lin, Sheng Chiang Hung, Feng-Ming Chang, Jui-Lin Chen, Ping-Wei Wang
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Patent number: 8461634Abstract: An integrated circuit device and method for manufacturing the same are disclosed. An exemplary device includes a semiconductor substrate having a substrate surface; a trench isolation structure disposed in the semiconductor substrate, the trench isolation structure having a trench isolation structure surface that is substantially planar to the substrate surface; and a gate feature disposed over the semiconductor substrate, wherein the gate feature includes a portion that extends from the substrate surface to a depth in the trench isolation structure, the portion being defined by a trench isolation structure sidewall and a semiconductor substrate sidewall, such that the portion tapers from a first width at the substrate surface to a second width at the depth, the first width being greater than the second width.Type: GrantFiled: April 14, 2011Date of Patent: June 11, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Lie-Yong Yang, Sheng Chiang Hung, Kian-Long Lim, Ping-Wei Wang
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Patent number: 8441829Abstract: SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor.Type: GrantFiled: March 19, 2010Date of Patent: May 14, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Huai-Ying Huang, Yu-Kuan Lin, Sheng Chiang Hung, Feng-Ming Chang, Jui-Lin Chen, Ping-Wei Wang
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Patent number: 8330227Abstract: A SRAM device with metal gate transistors is provided. The SRAM device includes a PMOS structure and an NMOS structure over a substrate. Each of the PMOS and the NMOS structure includes a p-type metallic work function layer and an n-type metallic work function layer. The p-type work metallic function layer and the n-type metallic work function layer form a combined work function for the PMOS and the NMOS structures.Type: GrantFiled: February 17, 2010Date of Patent: December 11, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng Chiang Hung, Huai-Ying Huang, Ping-Wei Wang
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Publication number: 20120261726Abstract: An integrated circuit device and method for manufacturing the same are disclosed. An exemplary device includes a semiconductor substrate having a substrate surface; a trench isolation structure disposed in the semiconductor substrate, the trench isolation structure having a trench isolation structure surface that is substantially planar to the substrate surface; and a gate feature disposed over the semiconductor substrate, wherein the gate feature includes a portion that extends from the substrate surface to a depth in the trench isolation structure, the portion being defined by a trench isolation structure sidewall and a semiconductor substrate sidewall, such that the portion tapers from a first width at the substrate surface to a second width at the depth, the first width being greater than the second width.Type: ApplicationFiled: April 14, 2011Publication date: October 18, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Lie-Yong Yang, Sheng Chiang Hung, Kian-Long Lim, Ping-Wei Wang
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Publication number: 20110241127Abstract: The present disclosure relates to methods for fabricating a field-effect transistor. The method includes performing a pocket implantation to a semiconductor substrate; thereafter forming a polysilicon layer on the semiconductor substrate; and patterning the polysilicon layer to form a polysilicon gate. The field-effect transistor (FET) includes a well of a first type dopant, formed in a semiconductor substrate; a metal gate disposed on the semiconductor substrate and overlying the well; a channel formed in the semiconductor substrate and underlying the metal gate; source and drain regions of a second type dopant opposite from the first type, the source and drain regions being formed in the semiconductor substrate and on opposite sides of the channel; and a pocket doping profile of the first type dopant and being defined in the well to form a continuous and uniform doping region from the source region to the drain region.Type: ApplicationFiled: May 28, 2010Publication date: October 6, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sheng Chiang Hung, Huai-Ying Huang, Ping-Wei Wang
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Publication number: 20110198699Abstract: A SRAM device with metal gate transistors is provided. The SRAM device includes a PMOS structure and an NMOS structure over a substrate. Each of the PMOS and the NMOS structure includes a p-type metallic work function layer and an n-type metallic work function layer. The p-type work metallic function layer and the n-type metallic work function layer form a combined work function for the PMOS and the NMOS structures.Type: ApplicationFiled: February 17, 2010Publication date: August 18, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sheng Chiang Hung, Huai-Ying Huang, Ping-Wei Wang