Patents by Inventor Sheng-Chiech Liang

Sheng-Chiech Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Circuit for correcting an output clock frequency in a receiving device
    Patent number: 8135105
    Abstract: An output clock correction circuit (14) for correcting a frequency of an output clock in a receiving device (13) that receives data (16) and a time stamp component (18) includes an output clock feedback loop (20), a FIFO buffer (22) and a time stamp adjuster (24). The output clock feedback loop (20) adjusts a phase and/or a frequency of the output clock based at least partially on the time stamp component (18). The FIFO buffer (22) temporarily stores the data (16). The time stamp adjuster (24) selectively adjusts the time stamp component (18) based on a status of the FIFO buffer (22). In one embodiment, the status is based at least in part on an actual data level in the FIFO buffer (22). In another embodiment, the FIFO buffer (22) has a target data level range, and the time stamp adjuster (24) adjusts the time stamp component (18) when the actual data level in the FIFO buffer (22) is outside this range.
    Type: Grant
    Filed: June 17, 2008
    Date of Patent: March 13, 2012
    Assignee: Integraded Device Technologies, Inc.
    Inventors: Zhibing Liu, Sheng-Chiech Liang
  • Circuit for correcting an output clock frequency in a receiving device
    Publication number: 20090310729
    Abstract: An output clock correction circuit (14) for correcting a frequency of an output clock in a receiving device (13) that receives data (16) and a time stamp component (18) includes an output clock feedback loop (20), a FIFO buffer (22) and a time stamp adjuster (24). The output clock feedback loop (20) adjusts a phase and/or a frequency of the output clock based at least partially on the time stamp component (18). The FIFO buffer (22) temporarily stores the data (16). The time stamp adjuster (24) selectively adjusts the time stamp component (18) based on a status of the FIFO buffer (22). In one embodiment, the status is based at least in part on an actual data level in the FIFO buffer (22). In another embodiment, the FIFO buffer (22) has a target data level range, and the time stamp adjuster (24) adjusts the time stamp component (18) when the actual data level in the FIFO buffer (22) is outside this range.
    Type: Application
    Filed: June 17, 2008
    Publication date: December 17, 2009
    Inventors: Zhibing Liu, Sheng-Chiech Liang