Patents by Inventor Sheng-Chieh Chen
Sheng-Chieh Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11956927Abstract: A case is provided, including a shell, a fan frame, and a fan module. The shell is internally provided with a backplane and a motherboard, where the motherboard is connected to the backplane along a first axis, the backplane is connected with a plug connector, the plug connector includes a plug connector body and a plurality of connection terminals, and the connection terminals are located in the plug connector body. The fan frame bears the fan module, and the fan module includes a fan assembly and a matching connector. The matching connector is connected to the fan assembly, and the matching connector is connected to the plug connector along a second axis. The matching connector includes a matching connector body and a plurality of matching terminals, and the matching terminals are located in the matching connector body. The fan frame is fixed in the shell.Type: GrantFiled: April 8, 2021Date of Patent: April 9, 2024Assignee: WISTRON CORPORATIONInventors: Jen-Hsien Lo, Wei-Hao Chen, Sheng-Chieh Tsai
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Patent number: 11948702Abstract: A radiation source apparatus includes a vessel, a laser source, a collector, a horizontal obscuration bar, and a reflective mirror. The vessel has an exit aperture. The laser source is configured to emit a laser beam to excite a target material to form a plasma. The collector is disposed in the vessel and configured to collect a radiation emitted by the plasma and to reflect the collected radiation to the exit aperture of the vessel. The horizontal obscuration bar extends from a sidewall of the vessel at least to a position between the laser source and the exit aperture of the vessel. The reflective mirror is in the vessel and connected to the horizontal obscuration bar.Type: GrantFiled: May 5, 2023Date of Patent: April 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-Chung Tu, Sheng-Kang Yu, Shang-Chieh Chien, Li-Jui Chen, Heng-Hsin Liu
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Publication number: 20240103378Abstract: The present disclosure provides an extreme ultraviolet (EUV) lithography system including a radiation source and an EUV control system integrated with the radiation source. The EUV control system includes a 3-dimensional diagnostic module (3DDM) designed to collect a laser beam profile of a laser beam from the radiation source in a 3-dimensional (3D) mode, an analysis module designed to analyze the laser beam profile, a database designed to store the laser beam profile, and an EUV control module designed to adjust the radiation source. The analysis module is coupled with the database and the EUV control module. The database is coupled with the 3DDM and the analysis module. The EUV control module is coupled with the analysis module and the radiation source.Type: ApplicationFiled: November 30, 2023Publication date: March 28, 2024Inventors: Tai-Yu CHEN, Tzu-Jung PAN, Kuan-Hung CHEN, Sheng-Kang YU, Shang-Chieh CHIEN, Li-Jui CHEN, Heng-Hsin LIU
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Patent number: 11915977Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked IC device also includes a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and a plurality of second conductive features formed in second inter-metal dielectric layers over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first conductive features and the second conductive features. The conductive deep-interconnection-plug is isolated by dielectric block, the first inter-metal-dielectric layers and the second inter-metal-dielectric layers.Type: GrantFiled: April 12, 2021Date of Patent: February 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Ting Tsai, Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Chih-Hui Huang, Sheng-Chau Chen, Shih Pei Chou, Chia-Chieh Lin
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Publication number: 20230207409Abstract: A semiconductor memory device and method of making the same are disclosed. The semiconductor memory device includes a substrate that includes a memory region and a peripheral region, a transistor including a metal gate located in the peripheral region, a composite dielectric film structure located over the metal gate of the transistor, the composite dielectric film structure including a first dielectric layer and a second dielectric layer over the first dielectric layer, where the second dielectric layer has a greater density than a density of the first dielectric layer, and at least one memory cell located in the memory region. The composite dielectric film structure provides enhanced protection of the metal gate against etching damage and thereby improves device performance.Type: ApplicationFiled: March 1, 2023Publication date: June 29, 2023Inventors: Sheng-Chieh CHEN, Wei-Ming Wang, Ming-Lun Lee, Chih-Ren Hsieh, Ming Chyi Liu
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Patent number: 11637046Abstract: A semiconductor memory device and method of making the same are disclosed. The semiconductor memory device includes a substrate that includes a memory region and a peripheral region, a transistor including a metal gate located in the peripheral region, a composite dielectric film structure located over the metal gate of the transistor, the composite dielectric film structure including a first dielectric layer and a second dielectric layer over the first dielectric layer, where the second dielectric layer has a greater density than a density of the first dielectric layer, and at least one memory cell located in the memory region. The composite dielectric film structure provides enhanced protection of the metal gate against etching damage and thereby improves device performance.Type: GrantFiled: September 14, 2021Date of Patent: April 25, 2023Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Sheng-Chieh Chen, Chih-Ren Hsieh, Ming-Lun Lee, Wei-Ming Wang, Ming Chyi Liu
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Patent number: 11600543Abstract: A semiconductor memory device and method of making the same are disclosed. The semiconductor memory device includes a substrate that includes a memory region and a peripheral region, a transistor including a metal gate located in the peripheral region, a composite dielectric film structure located over the metal gate of the transistor, the composite dielectric film structure including a first dielectric layer and a second dielectric layer over the first dielectric layer, where the second dielectric layer has a greater density than a density of the first dielectric layer, and at least one memory cell located in the memory region. The composite dielectric film structure provides enhanced protection of the metal gate against etching damage and thereby improves device performance.Type: GrantFiled: September 14, 2021Date of Patent: March 7, 2023Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Sheng-Chieh Chen, Chih-Ren Hsieh, Ming-Lun Lee, Wei-Ming Wang, Ming Chyi Liu
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Publication number: 20220274040Abstract: Provided herein are electret-MOF filter embedded with particles derived from metal-organic frameworks (MOF) and their methods of manufacturing. The methods of manufacturing the electret-MOF filter can include suspending MOF particles in a solvent to form a MOF particle mixture, contacting a charged polymeric fibrous web with the MOF particle mixture, and coating the charged polymeric fibrous web with the MOF particles by flowing the MOF particle mixture through an inverse side of the polymeric fibrous web. The disclosed coating method can deposit MOF particles uniformly, without formation of films at interstitial spaces between fibers. The electret-MOF filter can simultaneously remove fine particulate matters (PMs) and hazardous gaseous pollutants (including volatile organic compounds (VOCs)) with high particle holding and gas adsorption capacities, and with very low air resistance.Type: ApplicationFiled: November 6, 2020Publication date: September 1, 2022Inventors: Sheng-Chieh CHEN, Weining WANG, Xiang HE, Yu ZHANG
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Publication number: 20220270943Abstract: A semiconductor memory device and method of making the same are disclosed. The semiconductor memory device includes a substrate that includes a memory region and a peripheral region, a transistor including a metal gate located in the peripheral region, a composite dielectric film structure located over the metal gate of the transistor, the composite dielectric film structure including a first dielectric layer and a second dielectric layer over the first dielectric layer, where the second dielectric layer has a greater density than a density of the first dielectric layer, and at least one memory cell located in the memory region. The composite dielectric film structure provides enhanced protection of the metal gate against etching damage and thereby improves device performance.Type: ApplicationFiled: September 14, 2021Publication date: August 25, 2022Inventors: Sheng-Chieh CHEN, Chih-Ren HSIEH, Ming-Lun LEE, Wei-Ming WANG, Ming Chyi LIU
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Patent number: 11424255Abstract: A semiconductor device includes a substrate, an isolation feature, a floating gate, and a control gate. The substrate has a protruding portion. The isolation feature surrounds the protruding portion of the substrate. The floating gate is over the protruding portion of the substrate, in which a sidewall of the floating gate is aligned with a sidewall of the protruding portion of the substrate. The control gate is over the floating gate.Type: GrantFiled: February 11, 2020Date of Patent: August 23, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ming-Chyi Liu, Chih-Ren Hsieh, Sheng-Chieh Chen
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Patent number: 11296100Abstract: Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.Type: GrantFiled: June 23, 2020Date of Patent: April 5, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming Chyi Liu, Shih-Chang Liu, Sheng-Chieh Chen, Yu-Hsing Chang
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Publication number: 20220028985Abstract: Various embodiments provide a flash memory with an improved gate structure and a method of creating the same. The flash memory includes a plurality of memory cells that include a memory gate, a selection gate, a gate dielectric layer, and a protective cap formed on an upper surface of the gate dielectric layer. The protective cap protects the gate dielectric layer, and prevents the memory and selection gates from being unintentionally electrically connected to each other by conductive material.Type: ApplicationFiled: October 12, 2021Publication date: January 27, 2022Inventors: SHENG-CHIEH CHEN, MING CHYI LIU, SHIH-CHANG LIU
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Patent number: 11217596Abstract: Various embodiments provide a flash memory with an improved gate structure and a method of creating the same. The flash memory includes a plurality of memory cells that include a memory gate, a selection gate, a gate dielectric layer, and a protective cap formed on an upper surface of the gate dielectric layer. The protective cap protects the gate dielectric layer, and prevents the memory and selection gates from being unintentionally electrically connected to each other by conductive material.Type: GrantFiled: March 20, 2019Date of Patent: January 4, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sheng-Chieh Chen, Ming Chyi Liu, Shih-Chang Liu
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Patent number: 11171147Abstract: Various embodiments provide a flash memory with an improved gate structure and a method of creating the same. The flash memory includes a plurality of memory cells that include a memory gate, a selection gate, a gate dielectric layer, and a protective cap formed on an upper surface of the gate dielectric layer. The protective cap protects the gate dielectric layer, and prevents the memory and selection gates from being unintentionally electrically connected to each other by conductive material.Type: GrantFiled: March 20, 2019Date of Patent: November 9, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sheng-Chieh Chen, Ming Chyi Liu, Shih-Chang Liu
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Publication number: 20210249429Abstract: A semiconductor device includes a substrate, an isolation feature, a floating gate, and a control gate. The substrate has a protruding portion. The isolation feature surrounds the protruding portion of the substrate. The floating gate is over the protruding portion of the substrate, in which a sidewall of the floating gate is aligned with a sidewall of the protruding portion of the substrate. The control gate is over the floating gate.Type: ApplicationFiled: February 11, 2020Publication date: August 12, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ming-Chyi LIU, Chih-Ren HSIEH, Sheng-Chieh CHEN
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Patent number: 10903366Abstract: A process is provided to fabricate a finFET device. A gate electrode layer is positioned over a dielectric layer. The gate electrode layer and the dielectric layer are both positioned over and surrounding a fin-shaped semiconductor structure. A gate electrode is formed from the gate electrode layer through a two-step patterning process. At a first patterning step, an upper portion of the gate electrode layer is patterned. Then a dielectric film is formed covering the patterned upper portion of the gate electrode layer. After the dielectric film is formed, a second patterning process is performed to pattern a lower portion of gate electrode layer.Type: GrantFiled: September 17, 2019Date of Patent: January 26, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sheng-Chieh Chen, Ming-Chyi Liu
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Patent number: 10868028Abstract: An integrated circuit for a flash memory device with enlarged spacing between select and memory gate structures is provided. The enlarged spacing is obtained by forming corner recesses at the select gate structure so that a top surface with a reduced dimension of the select gate structure is obtained. In one example, a semiconductor substrate having memory cell devices formed thereon, the memory cell devices include a semiconductor substrate having memory cell devices formed thereon, the memory cell devices includes a plurality of select gate structures and a plurality of memory gate structures formed adjacent to the plurality of select gate structures, wherein at least one of the plurality of select gate structures have a corner recess formed below a top surface of the at least one of the plurality of select gate structures.Type: GrantFiled: December 11, 2019Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sheng-Chieh Chen, Ming Chyi Liu, Shih-Chang Liu
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Publication number: 20200321345Abstract: Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.Type: ApplicationFiled: June 23, 2020Publication date: October 8, 2020Inventors: Ming Chyi Liu, Shih-Chang Liu, Sheng-Chieh Chen, Yu-Hsing Chang
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Patent number: 10734394Abstract: Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.Type: GrantFiled: January 2, 2020Date of Patent: August 4, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming Chyi Liu, Shih-Chang Liu, Sheng-Chieh Chen, Yu-Hsing Chang
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Publication number: 20200144276Abstract: Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.Type: ApplicationFiled: January 2, 2020Publication date: May 7, 2020Inventors: Ming Chyi Liu, Shih-Chang Liu, Sheng-Chieh Chen, Yu-Hsing Chang