Patents by Inventor Sheng-Chih Yang

Sheng-Chih Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12185531
    Abstract: In some embodiments, the present disclosure relates to a memory device that includes gate electrode layers arranged over a substrate. A first memory cell is arranged over the substrate and includes first and second source/drain conductive lines that extend through the gate electrode layers. A barrier structure is arranged between the first and second source/drain conductive lines. A channel layer is arranged on outermost sidewalls of the first and second source/drain conductive lines. A first dielectric layer is arranged between the barrier structure and the channel layer. A memory layer is arranged on sidewalls of the channel layer. The first dielectric layer has a first maximum width measured between outermost sidewalls of the first dielectric layer. The first source/drain conductive line has a second maximum width measured between the outermost sidewalls of the first source/drain conductive line. The second width is greater than the first width.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: December 31, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Wei Jiang, Sheng-Chih Lai, Feng-Cheng Yang, Chung-Te Lin
  • Patent number: 12150275
    Abstract: The present disclosure provides an immersion cooling system for a server cabinet including a plurality of server boxes, a cooling tank and a plurality of liquid connecting pipes. Each server box includes an electronic device immersed in the cooling liquid, and the electronic device generates a thermal energy so that part of the cooling liquid evaporates into a hot vapor. The cooling tank is connected to the plurality of server boxes and includes a condenser and a storage part. The condenser is connected to each server box and condenses the hot vapor to form the cooling liquid. The storage part storages the cooling liquid from the condenser. Two ends of the liquid connecting pipe is connected to the storage part and the server box respectively. The cooling liquid in the storage part and the cooling liquid of each server box are maintained in a same liquid level.
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: November 19, 2024
    Assignee: Delta Electronics, Inc.
    Inventors: Li-Hsiu Chen, Ming-Tang Yang, Wei-Chih Lin, Peng-Yuan Chen, Sheng-Chi Wu, Ren-Chun Chang, Wen-Yin Tsai
  • Publication number: 20240379380
    Abstract: A system and method for generating a gas curtain over an access port of a processing chamber for a semiconductor substrate. A gas flow stabilizer and a gas flow receiver, each including a horizontal flow section and a vertical flow section cooperate to generate a gas curtain that impedes gas, e.g., oxygen, from outside the processing chamber, from flowing into the chamber, for example, when the access port is opened to add/or to remove a workpiece from the processing chamber.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Inventors: Sheng-Chun YANG, Po-Chih HUANG, Chih-Lung CHENG, Yi-Ming LIN, Chen-Hao LIAO, Min-Cheng CHUNG
  • Publication number: 20240381651
    Abstract: A semiconductor memory structure includes a ferroelectric layer and a channel layer formed over the ferroelectric layer. The structure also includes a source structure and a drain structure formed over the channel layer. The structure further includes a first isolation structure formed between the source structure and the drain structure. The source structure extends over the cap layer and towards the drain structure.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Inventors: Hung-Chang Sun, Sheng-Chih Lai, Cheng-Jun Wu, Yu-Wei Jiang, Feng-Cheng Yang, Chung-Te Lin
  • Publication number: 20240381630
    Abstract: In some embodiments, the present disclosure relates to a memory device that includes gate electrode layers arranged over a substrate. A first memory cell is arranged over the substrate and includes first and second source/drain conductive lines that extend through the gate electrode layers. A barrier structure is arranged between the first and second source/drain conductive lines. A channel layer is arranged on outermost sidewalls of the first and second source/drain conductive lines. A first dielectric layer is arranged between the barrier structure and the channel layer. A memory layer is arranged on sidewalls of the channel layer. The first dielectric layer has a first maximum width measured between outermost sidewalls of the first dielectric layer. The first source/drain conductive line has a second maximum width measured between the outermost sidewalls of the first source/drain conductive line. The second width is greater than the first width.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Inventors: Yu-Wei Jiang, Sheng-Chih Lai, Feng-Cheng Yang, Chung-Te Lin
  • Publication number: 20240334634
    Abstract: A parallel module driver is disclosed and includes a modular backplane structure, a rectifier module and an inverter module. The modular backplane structure includes a plurality of connectors arranged equidistantly in a first direction. The rectifier module includes a rectifier-connection slot connected to one of the plurality of connectors in a second direction. The inverter module includes an inverter-connection slot connected to one of the plurality of connectors in the second direction. The rectifier module and the inverter module are arranged adjacent to each other, the rectifier-connection slot and the inverter-connection slot are connected to two adjacent connectors on the modular backplane structure, respectively. The lateral sides of the rectifier module and the inverter module are attached to each other, and respectively include a guiding element and a guiding groove matched with each other and limiting the rectifier module and the inverter module to slide in the second direction.
    Type: Application
    Filed: June 13, 2023
    Publication date: October 3, 2024
    Inventors: Ching-Chi Yang, Hsien-Chung Lee, Kai-Ti Chang, Sheng-Chih Tsai, Tzu-Sen Hung
  • Publication number: 20240311542
    Abstract: A rectilinear-block placement method includes disposing a first sub-block of each flexible block on a layout area of a chip canvas according to a reference position, generating an edge-depth map relative to first sub-blocks of flexible blocks on the layout area, predicting positions of second sub-blocks of the flexible blocks with depth values on the edge-depth map by a machine learning model, and positioning the second sub-blocks on the layout area according to the predicted positions of the second sub-blocks of the flexible blocks.
    Type: Application
    Filed: December 27, 2023
    Publication date: September 19, 2024
    Applicant: MEDIATEK INC.
    Inventors: Jen-Wei Lee, Yi-Ying Liao, Te-Wei Chen, Kun-Yu Wang, Sheng-Tai Tseng, Ronald Kuo-Hua Ho, Bo-Jiun Hsu, Wei-Hsien Lin, Chun-Chih Yang, Chih-Wei Ko, Tai-Lai Tung
  • Publication number: 20240303408
    Abstract: The application discloses a method and a system for shaping flexible blocks on a chip canvas in an integrated circuit design. An input is received describing geometric features of flexible blocks. A set of flexible blocks are generated based on the input. Obtained block areas of the set of flexible blocks are computed. Whether the set of flexible blocks are legal is determined based on determining whether area differences between the obtained block areas and a plurality of required areas for the set of flexible blocks meet a requirement. The set of flexible blocks are updated until the set of flexible blocks are all legal.
    Type: Application
    Filed: March 7, 2024
    Publication date: September 12, 2024
    Inventors: Kun-Yu WANG, Sheng-Tai TSENG, Yi-Ying LIAO, Jen-Wei LEE, Ronald Kuo-Hua HO, Bo-Jiun HSU, Te-Wei CHEN, Chun-Chih YANG, Tai-Lai TUNG
  • Patent number: 12055228
    Abstract: A valve for throttling gas flow from a semiconductor processing tool includes a valve body. A shaft extends through the valve body. The shaft defines an internal cavity and a first opening communicating with the internal cavity. A first deflector is positioned on the shaft proximate the first opening and directed at a first interface between the shaft and the valve body. A method for throttling gas flow from a semiconductor processing tool includes providing a gas in an internal cavity defined in a shaft of a valve and directing the gas through an opening defined in the shaft and communicating with the bore toward an interface between the shaft and a valve body of the valve supporting the shaft.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: August 6, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Sheng-Chun Yang, Po-Chih Huang, Chang Chun, Xuan-Yang Zheng, Tzu-Chuan Chao, Ren-Jyue Wang, Yi-Ming Lin
  • Patent number: 12048164
    Abstract: A memory array and an operation method of the memory array are provided. The memory array includes first and second ferroelectric memory devices formed along a gate electrode, a channel layer and a ferroelectric layer between the gate electrode and the channel layer. The ferroelectric memory devices include: a common source/drain electrode and two respective source/drain electrodes, separately in contact with a side of the channel layer opposite to the ferroelectric layer, wherein the common source/drain electrode is disposed between the respective source/drain electrodes; and first and second auxiliary gates, capacitively coupled to the channel layer, wherein the first auxiliary gate is located between the common source/drain electrode and one of the respective source/drain electrodes, and the second auxiliary gate is located between the common source/drain electrode and the other respective source/drain electrode.
    Type: Grant
    Filed: January 9, 2023
    Date of Patent: July 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Ling Lu, Chen-Jun Wu, Ya-Yun Cheng, Sheng-Chih Lai, Yi-Ching Liu, Yu-Ming Lin, Feng-Cheng Yang, Chung-Te Lin
  • Publication number: 20090021126
    Abstract: A display panel is disclosed having a panel frame that holds cooling fans in an accommodation opening thereof and is provided with a locating groove and an engagement structure around the accommodation opening, a cover frame that has a locating flange fitted into the locating groove of the panel frame and an engagement structure detachably fastened to the engagement structure of the panel frame by hand without tools to lock the cover frame to the panel frame and ventilation ports corresponding to the cooling fans in the accommodation opening of the panel frame, filter members respectively mounted in the ventilation ports and held in place by respective positioning members for removing dust from air passing through.
    Type: Application
    Filed: July 18, 2007
    Publication date: January 22, 2009
    Inventors: Miao-Tzu Chou, Chia-Yen Hsu, Sheng-Chih Yang
  • Patent number: D786994
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: May 16, 2017
    Assignee: RAZOR USA LLC.
    Inventors: Robert Chen, Joey Huang, Sheng-Chih Yang, Ian Desberg