Patents by Inventor Sheng-Chou Lai

Sheng-Chou Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230387256
    Abstract: Various examples of a circuit device that includes gate stacks and gate seals are disclosed herein. In an example, a substrate is received that has a fin extending from the substrate. A placeholder gate is formed on the fin, and first and second gate seals are formed on sides of the placeholder gate. The placeholder gate is selectively removed to form a recess between side surfaces of the first gate seal and the second gate seal. A functional gate is formed within the recess and between the side surfaces of the first gate seal and the second gate seal.
    Type: Application
    Filed: August 10, 2023
    Publication date: November 30, 2023
    Inventors: Sheng-Chou Lai, Tsung-Yu Chiang
  • Patent number: 11830930
    Abstract: Various examples of a circuit device that includes gate stacks and gate seals are disclosed herein. In an example, a substrate is received that has a fin extending from the substrate. A placeholder gate is formed on the fin, and first and second gate seals are formed on sides of the placeholder gate. The placeholder gate is selectively removed to form a recess between side surfaces of the first gate seal and the second gate seal. A functional gate is formed within the recess and between the side surfaces of the first gate seal and the second gate seal.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: November 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sheng-Chou Lai, Tsung-Yu Chiang
  • Publication number: 20210280687
    Abstract: Various examples of a circuit device that includes gate stacks and gate seals are disclosed herein. In an example, a substrate is received that has a fin extending from the substrate. A placeholder gate is formed on the fin, and first and second gate seals are formed on sides of the placeholder gate. The placeholder gate is selectively removed to form a recess between side surfaces of the first gate seal and the second gate seal. A functional gate is formed within the recess and between the side surfaces of the first gate seal and the second gate seal.
    Type: Application
    Filed: May 17, 2021
    Publication date: September 9, 2021
    Inventors: Sheng-Chou Lai, Tsung-Yu Chiang
  • Patent number: 11011618
    Abstract: Various examples of a circuit device that includes gate stacks and gate seals are disclosed herein. In an example, a substrate is received that has a fin extending from the substrate. A placeholder gate is formed on the fin, and first and second gate seals are formed on sides of the placeholder gate. The placeholder gate is selectively removed to form a recess between side surfaces of the first gate seal and the second gate seal. A functional gate is formed within the recess and between the side surfaces of the first gate seal and the second gate seal.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: May 18, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sheng-Chou Lai, Tsung-Yu Chiang
  • Publication number: 20190165125
    Abstract: Various examples of a circuit device that includes gate stacks and gate seals are disclosed herein. In an example, a substrate is received that has a fin extending from the substrate. A placeholder gate is formed on the fin, and first and second gate seals are formed on sides of the placeholder gate. The placeholder gate is selectively removed to form a recess between side surfaces of the first gate seal and the second gate seal. A functional gate is formed within the recess and between the side surfaces of the first gate seal and the second gate seal.
    Type: Application
    Filed: September 7, 2018
    Publication date: May 30, 2019
    Inventors: Sheng-Chou Lai, Tsung-Yu Chiang