Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are described herein. A method includes forming a gate electrode, a gate electrode contact layer over the gate electrode, forming a dielectric layer over the gate electrode contact layer, and performing an etch through the dielectric layer, the etch forming an opening that exposes the gate electrode contact layer. The method further includes performing a post-etch treatment on the opening formed by the etch process by exposing the opening to a plasma. The method further includes forming gate electrode contacts in the openings after the post-etch treatment by a bottom-up deposition process.

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a silicon oxycarbonitride spacer, a silicon oxycarbide spacer, a silicon nitride spacer, and a source/drain structure. The gate structure is on the semiconductor substrate. The silicon oxycarbonitride spacer is on a sidewall of the gate structure. The silicon oxycarbide spacer is on a sidewall of the silicon oxycarbonitride spacer. The silicon nitride spacer is on a sidewall of the silicon oxycarbide spacer, in which an upper portion of the silicon nitride spacer has a lower density than a lower portion of the silicon nitride spacer. The source/drain structure is on the semiconductor substrate and adjacent to the gate structure.

Abstract: A method of forming a semiconductor device includes: forming a first conductive feature in a first dielectric layer disposed over a substrate; forming a second dielectric layer over the first dielectric layer; etching the second dielectric layer using a patterned mask layer to form an opening in the second dielectric layer, where the opening exposes the first conductive feature; performing an ashing process to remove the patterned mask layer after the etching; wet cleaning the opening after the ashing process, where the wet cleaning enlarges a bottom portion of the opening; and filling the opening with a first electrically conductive material.

Abstract: A method includes forming a gate structure on a semiconductor substrate; depositing a carbon-containing seal layer over the gate structure; depositing a nitrogen-containing seal layer over the carbon-containing seal layer; introducing an oxygen-containing precursor on the nitrogen-containing seal layer; heating the substrate to dissociate the oxygen-containing precursor into an oxygen radical to dope into the nitrogen-containing seal layer; after heating the substrate, etching the nitrogen-containing seal layer and the carbon-containing seal layer, such that a remainder of the nitrogen-containing seal layer and the carbon-containing seal layer remains on a sidewall of the gate structure as a gate spacer.

Abstract: A method for making a semiconductor device includes patterning at least one dielectric layer disposed over a conductive cap layer to form a via opening penetrating through the at least one dielectric layer to expose the conductive cap layer and to form a top portion of the conductive cap layer into a metal oxide layer; converting the metal oxide layer to a metal oxynitride layer by a soft ashing process using a processing gas containing nitrogen gas; removing the metal oxynitride layer from a remaining portion of the conductive cap layer; and forming a via contact in the via opening to electrically connect the remaining portion of the conductive cap layer.

Abstract: A package module includes an interposer, a plurality of semiconductor dies on the interposer, a module stiffener on the interposer adjacent to the plurality of semiconductor dies, and a molding material layer on the interposer around the plurality of semiconductor dies and the module stiffener.

Abstract: A shortcircuiting and circuit-breaking alarm includes a Darlington amplifier comprised of two NPN transistors connected in series, a PNP transistor connected to the Darlington amplifier, a first planar or linear conductor connected between a base of a first NPN transistor of the Darlington amplifier and a positive pole of a power source, a second planar or linear conductor connected between the Darlington amplifier and the PNP transistor having an insulator interposed between the first conductor and the second conductor, the first NPN transistor having its base connected to the positive pole of the power source through a resistor of large resistance, and the PNP transistor having its base connected to a negative pole of a power source through a resistor of small resistance, whereby upon a cutting of either the first or the second conductor or a shortcircuiting of the two conductors, the PNP transistor will be conducted to conduct a silicon control rectifier, which is connected to a sounding integrated circuit

Abstract: An alarming wallet includes: an alarm switch having two contactors respectively formed on two leaves of the wallet whereby upon a withdrawal of the wallet from an owner's pocket, the two contactors of the alarm circuit will be closed by a pickpocket's fingers to sound the alarm for alerting a wallet owner and preventing the theft of his or her wallet.

Abstract: A missing reminder for pocket article includes: a wallet for storing credit card or the like, a gravitational actuator clamped on the wallet and an alarming circuit which is operatively sensed when withdrawing the wallet from an owner's pocket by seating a weight disk of the actuator on a receiver to close two contacts of the alarming circuit formed on the receiver to sound the alarm and give warning to the wallet owner.