Patents by Inventor Sheng-Chun Ho

Sheng-Chun Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240114380
    Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a UE. In certain configurations, the UE establishes a connection supporting an extended reality (XR) application service with a base station. The UE reports, to the base station, a delay status report (DSR) to indicate a buffer size for data to be transmitted to the base station. The DSR includes timing information. The UE receives a configuration instruction from the base station. The UE configures resources on the UE according to the configuration instruction to transmit the data to the base station.
    Type: Application
    Filed: September 13, 2023
    Publication date: April 4, 2024
    Inventors: Ming-Yuan Cheng, Pradeep Jose, Chia-Chun Hsu, Sheng-Yi Ho
  • Publication number: 20160307799
    Abstract: The present disclosure relates to semiconductor substrates useful in semiconductor packages. In an embodiment, a semiconductor substrate comprises a patterned conductive layer, a patterned insulating layer, and a first protection layer. The patterned conductive layer has a first surface and a second surface opposite the first surface, and defines at least one space. The patterned insulating layer is disposed in the space, and has a third surface and a fourth surface opposite the third surface, where the third surface of the patterned insulating layer does not protrude from the first surface of the patterned conductive layer, and the patterned insulating layer comprises, or is formed from, a cured photo-sensitive resin. The first protection layer covers at least a portion of the second surface of the patterned conductive layer.
    Type: Application
    Filed: April 15, 2015
    Publication date: October 20, 2016
    Inventors: Sheng-Chun HO, Che-Yuan CHANG, Chung-Shou WU, Chi-Hsin LIN
  • Patent number: 6754951
    Abstract: A method of drilling a circuit substrate. A circuit substrate including at least a core layer and a metal layer covering one or both surfaces of the core layer is provided. A half-etching process is performed by etching the metal layer on the circuit substrate with an etchant to reduce the thickness of the metal layer. A surface treatment on the surface of the metal layer A via is formed in the circuit substrate by laser.
    Type: Grant
    Filed: July 31, 2001
    Date of Patent: June 29, 2004
    Assignees: Advanced Semiconductor Engineering Material, Inc., Advanced Semiconductor Engineering, Inc.
    Inventors: Sheng-Chun Ho, Min-Liang Hsiao
  • Publication number: 20020164836
    Abstract: A method of manufacturing a printed circuit board comprising the steps of: providing a substrate in which conductor circuits have been formed; forming a solder resist layer on the surface of the substrate; pre-curing the solder resist; imaging and developing the solder resist layer so as to form a desired solder resist pattern wherein a solder resist scum is remained on the substrate; post-curing the solder resist; and removing the solder resist scum. The solder resist scum removing step may be conducted by a permanganate desmearing process, a dichromate desmearing process, a plasma desmearing process, or a sand blasting process. The present invention further provides a method of improving the adhesion between a molding compound and a circuitized substrate with a solder resist layer formed thereon.
    Type: Application
    Filed: May 7, 2001
    Publication date: November 7, 2002
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING INC.
    Inventor: Sheng-Chun Ho
  • Publication number: 20020035785
    Abstract: A method of drilling a circuit substrate. A circuit substrate including at least a core layer and a metal layer covering one or both surfaces of the core layer is provided. A half-etching process is performed by etching the metal layer on the circuit substrate with an etchant to reduce the thickness of the metal layer. A surface treatment on the surface of the metal layer A via is formed in the circuit substrate by laser.
    Type: Application
    Filed: July 31, 2001
    Publication date: March 28, 2002
    Inventors: Sheng-Chun Ho, Min-Liang Hsiao