Abstract: A method for adaptively driving data transmission and a communication device using the same are provided. The proposed method includes following procedures. Detection result is generated after detecting a receiving signal on a receiving path of the communication device. Driving parameter is generated according to the detection result. Finally, a transmitting signal on a transmitting path is adjusted according to the driving parameter.

Abstract: A method for adaptively driving data transmission and a communication device using the same are provided. The proposed method includes following procedures. Detection result is generated after detecting a receiving signal on a receiving path of the communication device. Driving parameter is generated according to the detection result. Finally, a transmitting signal on a transmitting path is adjusted according to the driving parameter.

Abstract: The present invention provides a data memory controller that supports for the invert of data bus. Data transmitted from a memory is received in a chip set, which further transmits the data to a data processing apparatus. While receiving the memory data, the chip set doubles the bandwidth and reduces the frequency, such that the time margin for processing data is increased. In addition, after outputting data to the data processing apparatus, a first frame of data is compared to bus idle state to further reduce frequency of data invert and power consumption.

Abstract: The present invention provides a data memory controller that supports for the invert of data bus. Data transmitted from a memory is received in a chip set, which further transmits the data to a data processing apparatus. While receiving the memory data, the chip set doubles the bandwidth and reduces the frequency, such that the time margin for processing data is increased. In addition, after outputting data to the data processing apparatus, a first frame of data is compared to bus idle state to further reduce frequency of data invert and power consumption.

Abstract: The present invention provides a data memory controller that supports for the invert of data bus. Data transmitted from a memory is received in a chip set, which further transmits the data to a data processing apparatus. While receiving the memory data, the chip set doubles the bandwidth and reduces the frequency, such that the time margin for processing data is increased. In addition, after outputting data to the data processing apparatus, a first frame of data is compared to bus idle state to further reduce frequency of data invert and power consumption.

Abstract: A method for blocking a request to a front side bus interconnected between a central processing unit (CPU) and a control chip includes the following steps. First, a bus ownership of the control chip is assigned via a bus priority signal line. Any request from the CPU to the front side bus is blocked when the control chip owns the bus ownership. Meanwhile, any request from the control chip to the front side bus is inhibited when the CPU is blocked from outputting any request to the front side bus.

Abstract: A read/write scheduling apparatus of controller chip and method for the same. The read/write scheduling apparatus is used for arbitrating a plurality of read and write requests from a CPU to access a memory unit. The read request has higher priority in a host bandwidth limited case and the write requests in write queues are not sent until a predetermined amount of write requests are accumulated. In a DRAM bandwidth limited case, the read and the write requests have the same priority. The scheduling apparatus counts the number of the read and write requests to the memory unit within a predetermined time, the operation is changed to DRAM bandwidth limited case in case that the counted number is larger than a predetermined number.

Abstract: A control chip for accelerating the memory access and a method of operating the same is disclosed. The disclosed control chip receives a first address strobe (ADS) signal, a request signal, and an address bus signal from the CPU. A second ADS signal will be promptly issued if the selection phase of the request signal is either a memory read signal or a memory write signal and the address phase of the address bus signal indicates an effective memory address. Thereafter the second ADS signal is converted to a third ADS signal referring to the memory clocks. A memory control signal will be issued if no zero-length signal is suggested in length phase of the request signal and in the byte enable phase of the address bus signal. Computer system performances will be significantly upgraded since the third ADS signal is issued one cycle advanced than conventional approaches.

Abstract: A control chip having a multiple-layer defer queue therein and a method of operating the control chip. The control chip is coupled to a CPU bus and a PCI bus. The control chip comprises of a PC request queue, a multiple-layer defer queue, a PCI access queue and a PCI controller. The multiple-layer defer queue facilitates the processing of a multiple of concurrent CPU requests that belong to a first request type. The multiple-layer defer queue supports retry and defer transactions, thereby reducing data transmission between the CPU and the control chip.

Abstract: A method for blocking a request to a front side bus interconnected between a central processing unit (CPU) and a control chip includes the following steps. First, a bus ownership of the control chip is assigned via a bus priority signal line. Any request from the CPU to the front side bus is blocked when the control chip owns the bus ownership. Meanwhile, any request from the control chip to the front side bus is inhibited when the CPU is blocked from outputting any request to the front side bus.

Abstract: A read/write scheduling apparatus of controller chip and method for the same. The read/write scheduling apparatus is used for arbitrating a plurality of read and write requests from a CPU to access a memory unit. The read request has higher priority in a host bandwidth limited case and the write requests in write queues are not sent until a predetermined amount of write requests are accumulated. In a DRAM bandwidth limited case, the read and the write requests have the same priority. The scheduling apparatus counts the number of the read and write requests to the memory unit within a predetermined time, the operation is changed to DRAM bandwidth limited case in case that the counted number is larger than a predetermined number.

Abstract: A control chip for accelerating the memory access and a method of operating the same is disclosed. The disclosed control chip receives a first address strobe (ADS) signal, a request signal, and an address bus signal from the CPU. A second ADS signal will be promptly issued if the selection phase of the request signal is either a memory read signal or a memory write signal and the address phase of the address bus signal indicates an effective memory address. Thereafter the second ADS signal is converted to a third ADS signal referring to the memory clocks. A memory control signal will be issued if no zero-length signal is suggested in length phase of the request signal and in the byte enable phase of the address bus signal. Computer system performances will be significantly upgraded since the third ADS signal is issued one cycle advanced than conventional approaches.

Abstract: The present invention discloses a memory read/write arbitrating apparatus and method, which arbitrates a plurality of reading and writing requests from the CPU. The arbitrating apparatus includes a writing queue and a reading queue, a comparator, and an arbitrator. Before one writing request sending from CPU stored to the writing queue, the comparator compares the current writing request address with a previous one writing request address. Then, the comparison result and the writing request are stored in the writing queue. If the comparison result shows that the current writing request address belongs to the different memory page but to the same memory sub-bank with the previously executed writing request address and at least one reading request is present in the reading queue, the reading request will be executed preferentially.

Abstract: A control chip having a multiple-layer defer queue therein and a method of operating the control chip. The control chip is coupled to a CPU bus and a PCI bus. The control chip comprises of a PC request queue, a multiple-layer defer queue, a PCI access queue and a PCI controller. The multiple-layer defer queue facilitates the processing of a multiple of concurrent CPU requests that belong to a first request type. The multiple-layer defer queue supports retry and defer transactions, thereby reducing data transmission between the CPU and the control chip.

Abstract: The present invention provides a data memory controller that supports for the invert of data bus. Data transmitted from a memory is received in a chip set, which further transmits the data to a data processing apparatus. While receiving the memory data, the chip set doubles the bandwidth and reduces the frequency, such that the time margin for processing data is increased. In addition, after outputting data to the data processing apparatus, a first frame of data is compared to bus idle state to further reduce frequency of data invert and power consumption.