Abstract: A server system includes a PCH, a BMC, a BIOS with a write protect end, and a controlling circuit. The BIOS includes a write protect end. The BMC includes a memory portion storing updated server data. The BIOS is electrically connected to the PCH and is electrically connected to the BMC. The controlling circuit includes a first input end and an output end. The first input end is electrically connected to the PCH. The output end is electrically connected to the write protect end. The controlling circuit is configured so that when an error in the BIOS is detected, the write protect end is opened and the BIOS is updated from the memory portion of the BMC.

Abstract: An interface circuit applied in an electronic system includes a first control circuit and a second control circuit. The first control circuit includes a first control chip, a first voltage division unit, a switch unit, and a first connector. The second control circuit includes a second control chip, a second voltage division unit, a third voltage division unit, and a second connector. When the serial data pin or the serial clock pin first control chip outputs a first voltage level signal, the serial data pin or the serial clock pin second control chip receives the first voltage level signal. When the serial data pin or the serial clock pin first control chip outputs a second voltage level signal, the serial data pin or the serial clock pin second control chip receives a second voltage level signal from a power source terminal.

Abstract: An interface device includes a motherboard, a DVI female interface, a DVI male interface, a display, and an eSATA connector. The motherboard includes a SATA controller having at least one group of differential signal pins. The DVI female interface is electronically coupled to the group of differential signal pins. The DVI male interface is coupled to the DVI female interface. The display is electronically coupled to the DVI male interface. The eSATA connector is positioned on a display and includes at least one group of differential signal pins electrically coupled to the DVI male interface. The differential signal pins of the eSATA connector configured to be in communication with the differential signal pins of the SATA controller via the DVI male interface and the DVI female interface.

Abstract: A printed circuit board includes a baseboard, first and second conductive wires, a fuse, a 5V connector, a USB connector, and a CPU. The 5V connector is electrically connected to a first end of the fuse through the first conductive wire, and electrically connected to a voltage pin of the CPU voltage regulating chip through the second conductive wire. A voltage pin of the USB connector is connected to a second end of the fuse. The 5V connector outputs a 5V system voltage to the USB connector through the first conductive wire and the fuse, thus providing a voltage to a USB device, and also outputs the 5V system voltage to the CPU voltage regulating chip through the second conductive wire, thus signaling the CPU voltage regulating chip to convert the 5V system voltage and provide the converted voltage to a CPU.

Abstract: A server system includes a PCH, a BMC, a BIOS with a write protect end, and a controlling circuit. The BIOS includes a write protect end. The BMC includes a memory portion storing updated server data. The BIOS is electrically connected to the PCH and is electrically connected to the BMC. The controlling circuit includes a first input end and an output end. The first input end is electrically connected to the PCH. The output end is electrically connected to the write protect end. The controlling circuit is configured so that when an error in the BIOS is detected, the write protect end is opened and the BIOS is updated from the memory portion of the BMC.

Abstract: A method for testing Bit Error Rate (BER) of a network module of a communication device includes executing a BER test program to begin a BER test; obtaining a current time and a test data of the BER test program; recording the current time and the test data corresponding to the current time in the test data recording document. The method also determines whether a time interval between the current time and a time when a last test data was recorded is greater than a predetermined value, and if so records a new time and a new test data.

Abstract: A delay circuit for power sequencing in a computer includes an oscillator; an input pin; a counter; a register; and a comparing controller. The counter detects a voltage of the input pin when each clock signal arrives, resets a number counted by the counter when the voltage of the input pin is detected at logic-low electrical level, and adds a predetermined number when the voltage of the input pin is detected at logic-high electrical level. The controller compares the total number counted by the counter with a preset number, and outputs a control signal when the numbers match. The control signal controls a connected logic circuit to work according to a power sequence.