Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a magnetic tunneling junction (MTJ) on the first IMD layer; forming a liner on the MTJ and the first IMD layer; removing part of the liner to form a spacer adjacent to the MTJ; and forming a second IMD layer on the first IMD layer.

Abstract: A multimedia file recommending device capable of matching entertainment file to user mood or state includes an input device to receive emotional value X sensed from or inputted by a user, a storage device, and a processor. The storage device stores multimedia files each associated with an emotional value. The processor selects a multimedia file from the multimedia database according to default rules, wherein a difference between the emotional value associated with the selected multimedia files and the emotional value X falling within a preset range. A multimedia file recommending method is also provided.

Abstract: A gate driving circuit includes a shift unit and a switch unit. The shift unit receives a start input signal, a first clock input signal and a second clock input signal to generate an enable output signal. The switch unit is connected to the shift unit and receiving the enable output signal. The switch unit outputs a third clock signal based on the enable output signal.

Abstract: A driver circuit which includes an output circuit and a control circuit coupled to the output circuit. The driver circuit includes a pull-up transistor with a silicon semiconductor layer. The control circuit includes a first transistor with an oxide semiconductor layer.

Abstract: A gate driving circuit includes a shift unit and a switch unit. The shift unit receives a start input signal, a first clock input signal and a second clock input signal to generate an enable output signal. The switch unit is connected to the shift unit and receiving the enable output signal. The switch unit outputs a third clock signal based on the enable output signal.

Abstract: An assembly structure for an open-type tablet computer is disclosed. The open-type tablet computer comprises a computer main body which comprises base, a host system device, and a screen module exposed out of a front opening of the base. The assembly structure comprises locking members formed on a connection part around the base. When the computer main body is mounted on a fastening structure, the base can be embedded into a mounting hole of a body from the front of the fastening structure, and the connection part is stopped by the surface of a fastening part. The locking members can be inserted into a through hole of the body, respectively, and multiple jointing members can be locked, from a rear of the fastening structure, with the locking members, respectively. Therefore, the computer main body can be quickly aligned and assembled on with the fastening structure without extra mounting accessory.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate, a gate stack, and an interconnect structure over the gate stack and the semiconductor substrate. The semiconductor device structure also includes a resistive element over the interconnect structure, and the resistive element is directly above the gate stack. The semiconductor device structure further includes a thermal conductive element over the interconnect structure. The thermal conductive element at least partially overlaps the resistive element. In addition, the semiconductor device structure includes a dielectric layer separating the thermal conductive element from the resistive element.

Abstract: A driver circuit which includes an output circuit and a control circuit coupled to the output circuit. The driver circuit includes a pull-up transistor with a silicon semiconductor layer. The control circuit includes a first transistor with an oxide semiconductor layer.

Abstract: A display device including a panel having a gate driver is provided. The gate driver includes a multi-stage shift register. The N-th stage shift register includes a control module, a leakage compensation module, and an output module. The control module has a first terminal for receiving a first signal from the (N?M)-th stage shift register and a second terminal electrically connected to a node for transmitting a first signal to the node. The leakage compensation module has a third terminal electrically connected to the compensation voltage and a fourth terminal electrically connected to the node. The output module has a fifth terminal electrically connected to the node for receiving the first signal, and a sixth terminal for outputting a second signal of the N-th stage shift register for driving at least some parts of the pixel array. The compensation voltage charges the node during a touch sensing period.

Abstract: A method includes attaching a first semiconductor package on a carrier, wherein the first semiconductor package comprises a plurality of stacked semiconductor dies and a plurality of contact pads, depositing a first molding compound layer over the carrier, wherein the first semiconductor package is embedded in the first molding compound layer, forming a plurality of vias over the plurality of contact pads, attaching a semiconductor die on the first molding compound layer, depositing a second molding compound layer over the carrier, wherein the semiconductor die and the plurality of vias are embedded in the second molding compound layer, forming an interconnect structure over the second molding compound layer and forming a plurality of bumps over the interconnect structure.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate, a gate stack, and an interconnect structure over the gate stack and the semiconductor substrate. The semiconductor device structure also includes a resistive element over the interconnect structure, and the resistive element is directly above the gate stack. The semiconductor device structure further includes a thermal conductive element over the interconnect structure. A direct projection of the thermal conductive element on a main surface of the resistive element extends across a portion of a first imaginary line and a portion of a second imaginary line of the main surface. The first imaginary line is perpendicular to the second imaginary line. The first imaginary line and the second imaginary line intersect at a center of the main surface. The semiconductor device structure includes a dielectric layer separating the thermal conductive element from the resistive element.

Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a chip, a molding compound, and a dielectric layer. The chip has a connector thereon. The molding compound encapsulates the chip, wherein a surface of the molding compound is substantially lower than an active surface of the chip. The dielectric layer is disposed over the chip and the molding compound, wherein the dielectric layer has a planar surface, and a material of the dielectric layer is different from a material of the molding compound.

Abstract: A touch display device at least including a gate driver is provided. The gate driver at least includes a pull-up control circuit, a pull-down control circuit and a pull-up output circuit. The pull-up control circuit sets the voltage level of a first node to a first voltage level. The pull-down control circuit is configured to set the voltage level of the first node to a second voltage level and includes a first transistor receiving an operation voltage. The second voltage level is lower than the first voltage level. The pull-up output circuit generates a scan signal according to the voltage level of the first node. During a first display period and a second display period, the operation voltage is equal to a first gate voltage. During a touch-sensing period, the operation voltage is equal to a second gate voltage that is lower than the first gate voltage.

Abstract: A display device includes a pixel array, multiple data lines, and multiple gate lines. The pixel array includes multiple pixel units. The data lines are coupled to the pixel array. The gate lines are coupled to the pixel array. One of the pixel units includes a switch circuit, a display unit, and a first voltage level shifting circuit. The switch circuit is coupled to one of the data lines and one of the gate lines. The first voltage level shifting circuit is coupled between the switch circuit and the display unit and configured to adjust the voltage level of a data driving signal provided by the data line to the display unit.

Abstract: A millimeter wave filter fine-tuning structure includes a resonant cavity, a fine-tuning cavity disposed at the edge of the resonant cavity, a fine-tuning cavity coupled to the resonant cavity, and plural adjusting screws disposed and inserted in the fine-tuning cavity, and the distance between the adjusting screws and the resonant cavity may be used to adjust the resonant frequency of the filter.

Abstract: A method for controlling operating modes of a hybrid powertrain mechanism including a first epicyclic train having first and second sun gears and a planetary gear couplable to these sun gears; a second epicyclic train having third and fourth sun gears and a planetary gear couplable to these sun gears; a first electric machine having one end coupled to the second sun gear; a second electric machine having one end coupled to the fourth sun gear; a first clutch having one end coupled to another end of the first electric machine; a first brake having one end coupled to another end of the first clutch and another end coupled to the third sun gear; and an engine coupled to the first sun gear. Various driving modes are provided by changing the states of the first clutch and the first brake and the operating modes of the first and second electric machines.

Abstract: Embodiments of methods and apparatuses for resource allocation in a wireless communication system are disclosed. In one embodiment, a method of wireless communication comprises obtaining data to be transmitted over a plurality of sub-channels in a wireless communication environment, determining channel conditions associated with the plurality of sub-channels, scheduling the data to be transmitted according to the channel conditions associated with the plurality of sub-channels to form scheduled data for transmission, and transmitting the scheduled data to one or more receivers via the plurality of sub-channels. The method of determining channel conditions associated with the plurality of sub-channels comprises determining interference observed at each sub-channel in the plurality of sub-channels.

Abstract: A semiconductor device including a substrate having a major surface. The semiconductor device further includes a dielectric material on the major surface of the substrate. The semiconductor device further includes a first plurality of fins extending from the major surface of the substrate, wherein the dielectric material surrounding each fin of the first plurality of fins has a first thickness. The semiconductor device further includes a second plurality of fins extending from the major surface of the substrate, wherein a first fin of the second plurality of fins is on a first side of the first plurality of fins, a second fin of the second plurality of fins is on a second side of the first plurality of fins opposite the first side, the dielectric material surround each fin of the second plurality of fins has a second thickness, and the second thickness is different from the first thickness.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate, a gate stack, and an interconnect structure over the gate stack and the semiconductor substrate. The semiconductor device structure also includes a resistive element over the interconnect structure, and the resistive element is directly above the gate stack. The semiconductor device structure further includes a thermal conductive element over the interconnect structure. A direct projection of the thermal conductive element on a main surface of the resistive element extends across a portion of a first imaginary line and a portion of a second imaginary line of the main surface. The first imaginary line is perpendicular to the second imaginary line. The first imaginary line and the second imaginary line intersect at a center of the main surface. The semiconductor device structure includes a dielectric layer separating the thermal conductive element from the resistive element.

Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a chip, a molding compound, and a dielectric layer. The chip has a connector thereon. The molding compound encapsulates the chip, wherein a surface of the molding compound is substantially lower than an active surface of the chip. The dielectric layer is disposed over the chip and the molding compound, wherein the dielectric layer has a planar surface, and a material of the dielectric layer is different from a material of the molding compound.